Design Engineer

Cell: 510-***-****

Email: ************@*****.***

Addr: 43273 Livermore Com,

Fremont CA 94539

Hung Cheung

Objective

Proficient Professional eager to contribute technical expertise as well as strong engineering skills in a challenging ASIC, FPGA, and hardware design assignment actively supporting an organization in maximizing performance.

Career Profile

• Over 10 years of combined relevant ASIC, FPGA, and hardware design experience.

• Expertise in all facets of systems architecture procedures/methodologies.

• Proven experience to realize DSP algorithms into RTL/FPGA hardware.

• Proven testing and troubleshooting capacity to bring up board/system.

• Leading role in test bench design and RTL/FPGA design.

• Proficient in ASIC/FPGA/Hardware architecture, design, implementation, testing, verification and system integration.

• Fluent in C/C++ development including C modeling and embedded firmware design

• Strong focus on exceptional customer service/support, quality and meeting organizational objectives.

• Contributor in increasing proficiency in challenging environments.

• Adept in aligning IT contributions with organizational objectives.

• B.Sc., Electronics

• U.S. citizen.

Technology Skills

• Verilog/VHDL code development, Cadence VCS simulation tools, Synopsys synthesis tool, Debussy tool

• Altera FPGA development tools (Quartus II)

• C/C++ code development (Visual Studio, Unix C, Keil), Java, Java script, TCL, JTAG debugger

• Protel layout tool, ORCAD schematic capture

• Lab equipment: oscilloscope, logic analyzer, signal generator etc

Experience

Broadcom Corp. Sunnyvale, CA 2010-now

Application Engineer

Responsibilities include:

Documentation preparation. Drafting all product related document including datasheet, programming guide, application notes, etc.

ASIC verification. To verify ASIC verification after chip come back.

Eastman Kodak Corp. Sunnyvale, CA 2004-2009

System Design Engineer

Projects include:

ISP system for image sensor. ISP platform for a non-Bayer image sensor which serves as a design test and demo platform. Demonstrated in 6th sense show 2008.

• Profiling arithmetic intensive blocks (anti-shaking block, video stabilization block), determine time critical path and design hardware accelerator to improve the performance. Using fixed point arithmetic to implement all arithmetic blocks.

• Microarchitected/designed/coded in verilog for imaging pipe including blocks: sigma filter, median filter, blur filter, PNU filter, color interpolation, color rectification, auto white balance, auto exposure, lenshading correction, pink sky correction, edge sharpening, color correction, flicker detection, anti-shaking, video stabilization.

• Leading test bench design/debug for all individual blocks and the overall system. Created bit-accurate C model for all blocks. Compared C model and verilog block result. Debug/bring up the whole imaging pipe with FPGA board.

• Ported CPU8051 (Cast), architected/designed/coded for I2C, SPI, interrupt controller, timers, and related peripheral blocks. Test bench design/debug for all these blocks.

• Synthesis whole design into Altera Stratix II product (EP2S180).

• Designed/synthesized a FPGA to stream video to high definition TV encoder.

• Architected board design, debug and brought up the FPGA demo board

SOC CMOS image sensor product development. Bayer image sensor SOC product. Successfully tapeout, silicon verification.

• Architected board design, debug and bring up the FPGA demo/test board

• Evaluated/ported 3rd party IP (Cast CPU 8051) into silicon, ported FS2 CPU debugged block (CPU JTAG debug interface), designed/coded firmware downloading mechanism, designed/coded chip testing mechanism, and silicon verification.

• CPU instruction test design for CPU 8051 pre-silicon and post-silicon verification.

• Synthesis blocks with Synopsys tools.

• Ported digital part of whole design into FPGA (Altera Cyclone device). Performed pre-silicon verification with FPGA board before tapeout.

• Silicon verification for CPU block and related peripheral blocks.

USB interface board. Upload board to upload video stream to PC through USB. Major function is to do traffic control for video streaming with a SDRAM as memory buffer.

Designed a board with a Cypress USB controller.

Designed/coded logic traffic control among SDRAM, USB controller and video stream input. Designed a SDRAM controller to interface SDRAM.

Coded a firmware (8051 in USB controller) to interface a video interface and the USB.

National Semiconductor Corp. Sunnyvale, CA 1996–2004

Application Engineer

Projects include:

Digital auto back mirror system. A demo unit to demonstrate the SERDES IC and image sensor IC functionalities. This demo unit is used by marketing as a demonstration unit for their clients.

• Architected/designed/coded by verilog whole interfaces between image sensor and SERDES, SERDES and NTSC encoder. Test bench design for individual digital block. Synthesis whole design by Synopsys

• Ported whole design into Altera FPGA Cyclone device.

• Board level design including dc to dc power supply, LVDS circuit design

• Designed boards by ORCAD, layout boards by Protel.

• Coded control program to controlling the whole system.

Camera system. A demo unit to demonstrate the image sensor functionalities and all the camera controller functionalities including the controlling software using CR16 CPU. This demo unit is used by marketing as a demonstration for their clients.

• Designed/coded a FPGA for interfacing with a TFT display. Test bench design for overall system.

• Synthesis the blocks with Synopsys tools.

• Architected/designed boards of the whole system, created PCB layout for the boards.

TFT display controller. One of the peripheral blocks of CR16 CPU.

Designed block by using verilog,

Synthesis whole block by Synopsys.

Port whole block to Altera FPGA and verified the block.

• Designed a board to interface with a TFT display, created PCB layout for the boards.

• Coded control program for controlling the whole system.

Wireless baseband processor. A customized product for client, successfully tape out the chip.

Architected the whole silicon with the necessary AMBA peripherals blocks such as timer, interrupt controller, I2C, SPI interface etc. with the porting CPU from Xtersa.

Interfaced with customer to accommodate their needs and changes in the design.

A customized CR16 processor. Successfully delivered the product to client from concept to chip out.

Developed silicon verification programs (assembly code), and verified the silicon.

Interfaced with customers and provided training.

Education Chinese University of Hong Kong Hong Kong

B.Sc., Electronics

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