RAMJIKIRAN BALLA

**-*-**, * * pur,

Gollila peta, Email: ty9s5a@r.postjobfree.com.

Kakinada, AP 533002 Mobile: +91-996******* _______________________________________________________________________

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDLs: Verilog and VHDL

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Functional Coverage Verification

TB Methodology: VMM from Synopsys

EDA Tool: Modelsim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis.

Professional Qualification

• Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

• A+ Hardware and from Indian Institute of Hardware Technology (IIHT)

Kakinada branch.

Degree College/School

Board/University

Year of

Passing

Aggregate Master of Science and technology (MSc(Tech))in vlsi design

Andhra University

Andhra University

Vizag, AP

2011

7.48

Bachelor Degree in Electronics

Aditya degree collage

Board of

Intermediate, AP

2008

58

Achievements

Department Event Coordinator, Andhra university.(August 2009-May 2011).

Certified Training Courses

Maven Silicon Certified VLSI-RN (RTL to NetList) course from Maven Silicon, Bangalore. Jan, 2011-May, 2011

VLSI Projects

An FPGA Implementation of 30Gbps Security Module for GPON Systems:-

Organization : AU CAMPUS (Academic Project in 6th Semester)

Team Size : 2

HDL : VHDL

EDA Tools : Xilinx ISE

GPON systems require gigabit throughput data encryption for security and privacy. This paper presents an implementation of very high speed security module for GPON on Virtex4 FPGA. The security module supports payload encryption with constant delay by using counter mode AES algorithm. Our design of AES has three advanced features: composite field arithmetic Sub Byte, efficient Mix Column transformation, and On-the-Fly Key-Scheduling. Full-pipelined architecture is employed for the AES architecture in order to achieve the high performance for security module. The experiment shows that the proposed architecture can achieve a throughput of 30Gbits/s on a Xilinx Virtex-4 VLX100-12 device. The performance of our design is well suitable for encryption applications of GPON systems

Vending machine controller:

Organization : AU CAMPUS (Academic Project in 4th Semester)

Team Size : 2

HDL : VHDL

EDA Tools : Modelsim, Questa – Verification Platform and ISE

Implemented the vending machine controller using VHDL

Verified the RTL module using ISE

Writing test cases for output

Traffic light controller:

Organization : AU CAMPUS

Team Size : 1

HDL : VHDL

EDA Tools : Modelsim, Questa – Verification Platform and ISE

Traffic signal controller is playing more and more important roles in modern management and controls of urban traffic to reduce the accident and traffic jam in road. They assign the right of way to road users by the use of lights in standard colors (Red - Amber - Green), using a universal color code (and a precise sequence, for those who are color blind).

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Organization: Maven Silicon

Team size: 2 members

Duration: 15 days

Implemented the Real Time Clock using Verilog HDL independently

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

Dual Port RAM – RTL design and verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Organization: Maven Silicon

Team size: 2 members

Duration: 1 week

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Video Graphics Adaptor – RTL Design and Verification:-

Organization : MAVEN SILICON

Team Size : 1

Duration : 10 days

HDL : Verilog

EDA Tools : Modelsim, Questa – Verification Platform and ISE

Architected the design

Implemented the RTL using Verilog HDL

Verified the RTL using Verilog HDL

Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board

Contribution:

Analysis of the requirements.

Involved in the design and development of the backend code.

Preparing hardware circuit boards and testing

Analysis of components used in a project.

Preparing appropriate documents related to the project

Experience:

2011 Jan – 2011 May Maven Silicon, Bangalore - Trainee Engineer

The responsibility of this role is to design VLSI projects in Verilog and to verify them in both Verilog and System Verilog.

Written Verilog code and implemented on the FPGA board.

Written Verilog code and verified in both Verilog and System Verilog

PERSONAL DETAILS:

Date of Birth : 20th June, 1986

Father’s name : B.Sreeramulu

Sex : Male

Marital Status : Single

Languages Known : English, Hindi and Telugu.

Hobbies : Playing Caroms, Solving Sudoku, Listening Music.

Passport : J5117957

DECLARATION:

I, B.RAMJIKIRAN do hereby confirm that all the above mentioned information is true and to the best of my knowledge.

Place: Kakinada

Date:

(B.RAMJIKIRAN)

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