Engineer

**** *.**** ***** **. • CHICAGO, IL *****

PHONE 773-***-**** • E-MAIL **********@***.**

SVETLINA PENCHEVA

OBJECTIVE

Electronics engineering with interest in an analog and digital Design and Development and opportunity to use skills in Verilog, VHDL, Cadance, OrCAD and Pspice.

EDUCATION

2006 – up today Illinois Institute of Technology (IIT) Chicago

Advanced Electronics- Certificate program

• Introduction of VLSI Design

• Electron Devices

• Analysis and Design of Analog Integrated Circuit

• Active Filter Design

2002 – 2005 Technical University of Sofia Sofia, Bulgaria

Microelectronics- Master of Science degree; not completed thesis work. Major Areas of Studies:

• Functional Microelectronics

• VLSI Design

• Computer Simulation of Electronic Circuits

1998 – 2002 Technical University of Sofia Sofia, Bulgaria

Electronics- Bachelor of Science degree..

TRAINING/PROJECTS

Illinois Institute of technology – project

• Design and Synthesis of an 8-Bit Pipelined CPU using Verilog HDL. The project included the development of ALU, buffers, multiplexers, latches etc. The layout was tested using IRSIM.

Practical PCB training in EPIQ Electronic Assembly – 12 weeks

• Manual and automated assembly of electronic components on PCB.

• Module assembly: attaching the circuit board to other part, such as plastic housing

• Chip on board assembly

Practical training in ECAD Laboratory of Technical university of Sofia - 2 years

• Design CMOS Sub-Bandgap Voltage reference with stable output parameters at variation of temperature, power supply and technology parameters using PSpice and CADANCE. Two technologies are used: AMS 0.35μ Si CMOS and AMS 0.8μ SiGe BiCMOS.

• PCB Layout

• Layout of Bandgap Voltage Reference of AMS 0.8µ SiGe BiCMOS technology

COMPUTER SKILLS

• CAD programs:

- Schematic capture tools and PCB layout (OrCAD, PSpice, CADANCE, Mentor Graphics);

- VHDL and Verilog programming;

• Windows, Microsoft Word, Microsoft Excel;

• Programming Skills – C, C++, Pascal.;

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