Interdisciplinary Design Engineer
Resume:
Resume: Ivan Batinic
*.*.*******@*****.***
Objective: To engage in and impel collective product development; concept-to-market
under time-to-market duress with a sense of responsibility for ROI are what define
my element.
Skills:
HW: Mixed Signal, Discrete Analog, Linear, RF, HS Digital, Embedded Control,
DFT (BIST/MBIST/BISR/BOST), DSP, HDL/RTL (Verilog/VHDL/System C),
FPGA/FPAA, ASIC/SoC, FSM, SIMD/MIMD, PCB, ATE/T&M instr. design
SW: Assembler/uCode, Scripting SH/PERL/TCK/PYTHON, OOP, OODA, C/C++,
PLCs, EDA/Simulator/GUI/OS dev., UNIX/MSWindows/MFC/VxWORKS/RTOS
FW: Proprietary microcode, embedded control, target code em., custom O/S dev.
Optical: Prototyping: Bench stages, beam forming, positioning, focusing, modulation,
CCD/LASER/FIBER/SM/MM, multi-ported scopes/objectives, dichroic filters,
Co-axial multi-lambda beam multiplexing, couplers, collimators, terminations
Admin: Bilingual (native English, fluent French), engaging technical presentations,
Post-graduate level technical writing, dept. management & technical leadership
Experience:
Jan '09 Advanced Tire Pressure Systems Inc. (Automotive IP Provider) Troy, MI
Present Chief Technology Officer, Principal Engineer
* Designed real-time vehicle component integrity monitor for military market
* Reviewed 3,000+ patents regarding TPMS (Tire Pressure Monitoring System)
* Steered the company's technological development toward the current solution
* Designed, characterized and patented "magneto-pneumatic" non-RF TPMS
* Specified mobile data-logger with cellular web upload for test vehicle fleet
* Technical Liaison in multiple OEM vehicle mfr. and tier-1 vendor discussions
Oct '99 3rd Millennium Test Solutions Inc. (Configurable ATE Mfr.) San Jose, CA
Jan '09 System Architect, Principal Engineer
* Mixed Signal ATE backplane, 22 layers, -140dB noise floor (PADs)
* APG & Vector Engine, 24ch 200MHz (ASIC/FPGA 60M gates) (Verilog 2k)
* Sub-picosecond Time Measurement Unit SoC/FPGA core (Verilog 2k)
* 5 programmable precision supplies with V & I PID control, covering
1nA to 200A, 100uV to 2.5kV (CW & Pulsed), clamping, 2/4Q, buck/boost
* Prober Snorkel 400ch Analog channel mux, <10pA leakage (24 in3 pkg)
* Fault-Tolerant Memory Testhead, 400ch, 200MHz Duplex-voting (DRAM radiation
hardness characterization for spacecraft, operated inside beam-line
* Optical Testhead, 3-lambda XY Navigable for Blu-Ray(tm) pick-up device test
- Pioneered new beam forming and multiplexing methods
- Designed and machined custom optical stages
- Retrofitted 100mW SS NIR, RED & UV LASERS with programmable power
control and enhanced beam modulation from 20MHz to 100MHz
* Thermal Resistance testhead for Nissan IGBT module characterization (6kW)
* Analog Loop Testhead for low-noise, Hi-Fi linear small-signal device test
* 2 Test Vector processors, 16ch 100MHz FPGA (edge-placement to 0.5ns)
* High Performance AC Characterization (Step-Function/FFT)
* Verilog/PLI hooks enabling functional SW to drive HW co-simulation
* Auto-Calibration SW and GUIs (C++, Verilog)
* Principal or co-inventor on 8 potential patents (queued for application)
Jun '98 Credence Systems Corporation (VLSI ATE Mfr.) Fremont, CA
Oct '99 Manager & Technical Lead, DFT Development
* 13 patent applications, 4 Internationally allowed to date (Verilog, FPGA):
- BOST: FPGA MBIST APG, embedded memories (SoC, MCM, HDL, RTL)
- 3G MBIST (Programmable per-cycle pattern as scan-insertable wrapper)
- BISR (Self-Repair) Hi-Rel. DRAM can test & assign redundancy on power
* Led HW & SW dev. MBIST-Insertion EDA & IP (C++, MFC, Wind/U, Verilog)
* Designed custom MBIST for associative memories, FIFOs & ROMs (Verilog)
Feb '97 Heuristic Physics Laboratories, Inc. (Memory ATE Mfr.) Milpitas, CA
Jun '98 Manager & Technical Lead, Advanced Test Methodologies Development
* Managed DFT Division (15 engineers, 7 HW, 8 SW) (C++, VHDL, Verilog)
* Designed BIST logic and led its EDA tool development (Verilog, C++, MFC)
* Several app-specific embedded BIST solutions for SoC and ASICs (Verilog)
* Automated Timing and DC calibration methodologies for ATE platform (Rexx)
* 100MHz Algorithmic Pattern Generator (pipelined micro-programmable logic)
* 100MHz Pattern Capture Memory Subsystem (pipelined FPGA & SRAM)
[Credence Systems acquired HPL's DFT Division (see previous tenure above)]
Prior Work: Available upon request.
Education:
1991 University of California Extension, Sunnyvale, CA.
OOP/C++ Certification (C++ Founders Anderson/Klein)
1979 Heald Engineering College, San Francisco, CA.
BS/EE (challenged 1/2 curricula, pending accreditation)
AS/EE (4.0GPA)
1978 Teaching Assistant, PL/1 Optimizer, Dr. W. M. Farley, Stanford Linear
Accelerator Center, Menlo Park, CA
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