Manager Assistant
Resume:
Shilpa Subramanyappa
Buffalo, NY 14214
********@*******.***
Objective
Seeking a challenging career in ASIC/FPGA Design and Verification.
Education
MS, SUNY at Buffalo [CGPA: 3.6/4], Dec 2011
BE, Visveswaraiah Technological University, India ,Jun
Technical Skills
Programming Skills:C, Verilog, Assembly 8085, 8086, Perl (Basic level)
Simulation/EDA Tools:Cadence Virtuoso, Xilinx ISE, GDB.
Operating Systems:Windows 9X/NT/XP, Linux.
Documentation Software: MS Office, Adobe Pro
Academic Projects
1.MIPS Processor
a. Implemented a 32 bit, single cycle MIPS Processor supporting 12 instructions using verilog on a Basys 2 Board
b. The processor operated in four modes and displayed the result on a seven segment display.
2.Http Server
a. The server was implemented in C on UNIX based platform to serve requested files using HTTP
protocol.
b. Implemented the thread pool mechanism where a n number of threads were created to serve the
requests. Used semaphores and mutexes to achieve the synchronization between threads.
3.Virtual Memory Manager
a. Coded and simulated FIFO, LFU and SC page replacement algorithms in C on UNIX based
platform.
b. Designed 2.5V, 150mA linear Voltage Regulator circuit using Cadence Virtuoso.
4.Analog audio amplifier design with four digitally selectable gains using Cadence Virtuoso.
5.Design and layout of SRAM and NC-SRAM using Cadence Virtuoso.
6. A 4 bit calculator on FPGA board using verilog.
7.Undergraduate Project : Target Counter using ATmega 32 (IISC , Bangalore)
MS Courses
Computer Architecture, Operating systems, Introduction to Digital VLSI , Modern CMOS Devices, Analog Circuit
Design, Antennas and Mobile Communication.
Non academic Experience
Student Assistant at School of Dental Medicine, University at Buffalo.
Cashier/Front Line at Campus Dining and Jobs, University at Buffalo.
Front Office Assistant at Speak English, Bangalore.
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