Engineer Electrical

Brian Vaupel

PO Box *****

Rio Rancho, NM *****

Phone: 505-***-****

EMAIL: *******@*****.***

PROFILE: Electrical Engineer with over 12 years of experience with Integrated Circuit design, custom layout, component design, and rad-hard device Research and Development. Design work includes custom Analog layout, synthesis, place-and-route, and verification of blocks for ASIC implementation; and design, assembly, and testing of VCXO devices. Other background includes standard cell library development and development of new transistor designs for space applications. Able to communicate well with technical peers as well as non-technical. Obtained Secret Level Clearance in 2000.

SELECTED ACHIEVEMENTS

• Created, developed, and implemented new cell level libraries for in-house IC designs as well as external customers.

Owned development of new library creation, automating approximately 75% of the process, in order to reduce completion time from several months to approximately one week.

• Analyzed multiple designs of electronic components. Made design changes as per revised requirements, and successfully managed quick turn-around of re-designed parts.

• Worked with other engineers to develop new transistor layout methods to improve operation in radiation environments.

• Completed custom layout of PLL specifically designed for SET immunity, noise immunity, and compensation for discrepancies in critical path nodes.

PROFESSIONAL EXPERIENCE

Xilinx Inc, Albuquerque, NM Nov. 2007 – July 2011

Layout Designer

• Created custom layouts blocks such as POR, Memory Controller, System Monitor, System Security, and IO/ESD blocks for use in FPGA chips.

• Led layout design for 28 and 20 nm testchips. Was responsible for providing layouts of a concept that were DRC clean, and LVS clean to a manually created netlist.

• Created building blocks for new standard cell designs thus allowing layouts to be completed much quicker with fewer errors on first pass through design.

• Worked with circuit designers across sites to simplify designs in order to make final layout smaller.

ATK/MRTS Micro Electronics, Albuquerque, NM Feb. 2000 – Nov. 2007

Scientist/Engineer Level IV

• Designed and maintained layouts of primitive level cell libraries in addition to custom chip layouts. Full layout also included modification of existing chips to replace transistors while keeping the same footprint, design rule checking, and schematic versus layout verification.

• Led layout for custom designed PLL to be radiation hard for space application.

• Developed a process to characterize cell libraries for in-house designs as well as external customers. Automated characterization to be performed within 1 week instead of several months.

• Developed new layout techniques for radiation hardened transistors.

• Verified IC designs with various types of simulations. Updated designs as necessary to meet timing requirements as well as correct functionality.

• Performed synthesis and place-and-route of ASIC designs. Utilized RTL design to obtain chip level netlist and performed place and route to obtain full chip layout.

Connor Winfield, Aurora, IL Sep. 1998 – Jan. 2000

Engineer

• Managed 5 timing device projects. Took product from initial design or design modification, through prototype assembly and testing, mass production, and distribution to customers. Supervised 3 technicians for assembly and testing of components.

• Updated VCXO and CLOCK designs. Took existing designs and modified for new design requirements. Did initial modifications, tested modifications, and assembled new parts with surface mount components, die placement, wire-bonding, crystal mounting, and package sealing.

YOUTH ENCOUNTER, Minneapolis MN Aug. 1997 – Aug.1998

Volunteer

EDUCATION

B.S., Electrical Engineering GPA 3.2/4.0

Northern Illinois University, Dekalb IL 1997

A.A.S., Electronics Technology GPA 3.58/4.0

Kishwaukee Jr. College, Malta IL 1991

TECHNICAL QUALIFICATION and SOFTWARE EXPERIENCE

Cadence, Calibre, Lay-Ed, L-Edit, Synopsys, SVR Gards (place-and-route), Dracula, Diva, Spice, Silvaco, Lib-Tech, View Logic, Orcad, UNIX, Windows, Microsoft Word, Excel

PROFESSIONAL REFERENCES

NAME TITLE ORGANIZATION PHONE EMAIL

Cindy Begay Engineer Sandia Nat. Labs 505-***-**** ******@******.***

Tao Yu Process Engineer Xilinx 408-***-****

Howie Danzik Entrepreneur 719-***-**** ********@****.***

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