MTECH Graduate with 1 year experience in ASIC Front-end Design

RAJESH.R

E-mail: *******@*****.***

Address: #*, *** *****, *.*.A Layout,

Hulimavu, Bannerghatta Road, Bangalore-560076

Mobile: +919*********

Objectives

To work hard and efficiently in whatever task I undertake and achieve excellence in whatever job I do. Also accept challenges and move up the ladder of life with an aim to make the parent company a leader in the years to come and simultaneously grow in terms of expertise and experience

Educational Qualification

EXAM/COURSE INSTITUTION BOARD/UNIVERSITY YEAR

MTECH(DECSYS) PESIT, Bangalore VTU, Belgaum

2011

B.E(ECE) The Oxford College of Engineering, Bangalore Visvesvaraya Technological University

2009

PUC National College, Bangalore PU Board 2005

SSLC Bangalore High School, Bangalore KSEEB 2003

Technical Skills:

Language : Verilog, Basics of System Verilog,MATLAB, Basics of C, C++

Design Software/Tools : XILINX ISE 13.2, MATLAB R2008b, Modelsim,PSPICE.

Academic Projects/Presentations:

• ‘DESIGN AND DEVELOPMENT OF MICROCONTROLLER BASED DUAL CHANNEL ANALOG INPUT MODULE’

Project was carried out in British Instruments and Systems with the guidance of the Research Department in the company.

• Presentations on ‘ DYNAMIC SPECTRUM ACCESS NETWORKS & COGNITIVE RADIO’ and ‘ SPECTRUM SURVEY FRAMEWORK FOR DSA NETWORKS’.

• Implemented Wi-fi using MATLAB simulink software.

• Developed an Improved ‘LINEAR PARALLEL INTERFERENCE CANCELLATION’ (LPIC) for interference cancellation in a 3G system for cancelling CFO-induced multiuser interference.

COMPANY PROJECTS:

• Design and implementation of ‘REED-SOLOMON ENCODER/DECODER IPCORE’

Description:

Project is being carried out in Semtronics Microsystems Pvt Ltd. under the guidance of Mentor R&D.

Reed-Solomon encoder is a forward error correcting encoder which finds its application in DVB systems, satellite communication, storage systems etc..Developed Reed-Solomon encoder has least possible latency and was tested on SPARTAN 3E FPGA kit. This encoder has been developed for all possible symbol length and its core is customizable for user specifications.

Reed-Solomon decoder has been successfully designed and is in the verification stage.

Role: Front-end Design and Verification

Language used: Verilog, MATLAB

Tools used: Xilinx ISE 13.2, MATLAB7 R2008b

Team size: 3

Hardware platform: SPARTAN 3E FPGA tool kit

• Design and implementation of ‘ IEEE 802.15.4 ZIGBEE TRANSCEIVER’.

(Implementation under process)

Description:

IEEE 802.15.4/ZIGBEE is a standard which specifies the physical layer and media access control for low-rate wireless personal area networks. ZIGBEE is mainly used for control applications.

We have designed the RF transmitter part of ZIGBEE transceiver using verilog and implementation is currently under progress.

Role: Front-end Design

Language used: Verilog, MATLAB

Tools used: Xilinx ISE 13.2, MATLAB7 R2008b

Team size: 3

Hardware platform: SPARTAN 3E FPGA tool kit

• Currently working on design and implementation of ‘TURBO CODES’.

Work Experience:

• Working in ‘SEMTRONICS MICROSYSTEMS PVT. LTD.’ As a Trainee Engineer (R & D). (Oct-2011 to present).

Extra Curricular Activities:

• Represented the College Football and Cricket team in Inter-Collegiate Tournaments.

Declaration:

I Rajesh.R, hereby declare that the information furnished above is true to the best of my knowledge.

Date:

Place: Bangalore RAJESH.R

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