Design Engineer

***,******** ****,

Whitefield-******

Mob: +91-900*******

Email: ************@*****.***

JYOTI KASHYAP

Objective:

To work in a challenging environment where learning curve is higher and can employ my skills to the best towards VLSI design.

Achievements:

Awarded “Qualstar”, Qualcomm’s internal award for excellence in Quality of Work and

efforts in delivering QL45UHD library layouts in tight schedule.

Experience:XPT Software Pvt. Ltd.(Dec 2011 - till date)

I am working as Sr. Design Engineer for client Intel from XPT Software.

Experience: Masamb Electronics Systems(Sep 2010-Dec 2011)

I worked as Design Engineer in for client ST Microelectronics India Pvt. Ltd. from Masamb Electronics Systems.

Experience: Skyline Institute of Technology(Feb2009-Sep2010)

I worked as a lecturer in Skyline Institute of Technology.

Experience: Qualcomm India Pvt. Ltd.(Jan 2007 – Feb 2009)

I have 2+ years of experience in Standard Cell libraries for 45nm and 28nm technology at

Qualcomm CDMA Technologies (QCT).

Project Summary:

Responsibilities in ST Microelectronics/Intel:

• Responsible for standard cell, memory and I/O library views generation for different libraries.

• Responsible for Standard cell layout design as an individual contributor for 7 track Starlib and level shifter at 65nm technology.

• Responsible for physical design, development and verification of Standard Cells in various deep sub-micron technologies.

• Design and implement scripts required to automate parts of the Std. Cell IP development flow.

• Worked on double height retention flip flops at 45nm Technology for 12 and 9track.

• Worked on 28nm 12 track library from basic logic gates to combinational and sequential cells.

• Currently working on 28nm 9 track library from basic logic gates to combinational and sequential cells.

Responsibilities in Qualcomm:

Project Description:- Performance analysis of different architectures for 28nm.

Responsibilities:- Layout Design for 28nm library combinational and Sequential cells

migrated from 45nm library layout.

Project Description: - Design of Ultra High Density library for better performance

as compared to High Density library for 45nm to be used for targeted chip.

Responsibilities:- Layout design of scan flip flop, Non scan flip flops, High

speed flip flops, LCP flip flop and flop tray to reduce area up to 50%.

Project Description:- Design of High Density library for better performance as

Compared to TSMC library and to be used for targeted chip.

Responsibilities: - Layout design of Programmable Filler cells, CGC, Clock

Inverters, Clock Buffers, balanced cells with take care of PSE effect.

Project Description:-Design of High Performance library for better performance

As compared to TSMC library and to be used for targeted chip.

Responsibilities:- Layout design of Voltage Level Shifter, Ring Oscillator, multiple

Height cells.

Project Description:- R&D on 9 tracks to 8 tracks conversion library for 45nm

Technology.

Responsibilities:- Layout design and optimization of approximately 18-20 cells to

check the area comparison for migrated cells from 9 tracks library to 8 tracks library.

Industrial Training:-

ST Microelectronics India Pvt. Ltd. ( Jan 2003 to June2003)

Project Description: Circuit design, layout analysis and physical verification of complex combinational and sequential designs.

Technical Skills:

Operating System Windows 2003, XP, Linux

Tools Cadence Tools: Virtuoso Layout Editor and other in house tools.

Mentor Graphics Tools: Calibre for DRC,LVS,ERC and soft check etc.

Languages SKILL ,C,VHDL,Matlab

Education Details:

Post Graduation

M.Tech (VLSI Design) 2004 – 2006

C-DAC, Noida

Indraprastha University, Delhi, India

Percentage – 73.6%

Post Graduation

M.Sc.(Electronics) 2001 – 2003

Department Of Electronics Science, South Campus, Delhi, India

Percentage – 62%

Graduation

B.Sc.(Electronics) 1998 – 2001

Deen Dayal Upadhyaya College, Delhi University, India

Percentage – 64%

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