Curriculum Vitae

Name HARISANKAR.B.R

Mobile: +91-940*******

Residence:POORNAKRIPA,AMPADY THAZHAM LANE,

SREE POORNATHRAYEESA ROAD,

POONITHURA, ERNAKULAM

PIN: 682038

E-Mail: sgm0ur@r.postjobfree.com

OBJECTIVE

Looking for a promising & challenging career which will enable me to provide best of my analytical, technical & professional skills . A career which can sharpen my current skills and knowledge and where I can have a good scope for learning and implementing new technologies.

AN OVERVIEW

B.Tech – Electronics & Communication

Successfully completed project on Power Extracting Advanced Spy Militant using C & Assembly language

Well versed with Hardware, Software, Electronics, Semiconductor, etc.

Good understanding of VHDL, Verilog C, Assembly etc.

Proficiency at grasping new technical concepts quickly & utilizing it in a productive manner.

Believe in continuous learning and an innovative approach.

Adaptable and a quick learner; possesses skills to work under pressure.

Possesses good communication & interpersonal skills.

ACADEMIC CREDENTIALS

Completed P.G Diploma programme in VLSI & Embedded Hardware Design conducted by National Institute of Electronics and Information Technology, Calicut (formerly CEDTI, Calicut), an Autonomous Scientific Society of DIT, the Ministry of Communications and Information Technology, Govt. of India; involved in Training, R&D and Consultancy Services)

2011 Bachelors in Engineering – Electronics & Communication Engineering from Sree Narayana Gurukulam College of engineering Mahathma Gandhi University. Secured 64.5 % aggregate)

2007 H.S.C. from Bhavans Vidhya Mandir, CBSE Board. Secured 73%.

2003 S.S.C. from Bhavans Vidhya Mandir, CBSE Board. Secured 76%.

IT FORTE

Languages : C, Assembly, VHDL, Verilog HDL, Scripting (Perl/Tcl/Tk)

Operating System : Windows ,Linux

VLSI & Embedded System : FPGAs (Xilinx & Altera),Microcontroller(8051),PSoC

EDAs : Altera Quartus II,Xilinx ISE ,Modelsim SE,MATLAB,Keil C

Technical Skills:

Good Knowledge in Digital Logic Design

Good Knowledge in CMOS Logic Design

Good programming skills using Verilog HDL and VHDL

Basic Programming knowledge in C

Good knowledge in Xilinx and ALTERA FPGA Architectures

RTL Core design and development using Verilog HDL and VHDL for ASIC and FPGA Designs

Functional Verification using Modelsim

FPGA Synthesis using Xilinx ISE and ALTERA Quartus2

PROJECT 1

Title : Modified Power Saving Energy Meter

Durations : 1 month

Language : VHDL

Synopsis : The project was executed with:

Implementing the whole project on altera kit

Key learning : Learnt the basic concept digital electronics and VHDL

PROJECT 2

Title : RISC Processor

Durations : 1 month

Language : Verilog

Synopsis : The project was executed with:

Implementing the whole project on Altera kit using verilog and tested using test benches.

Key learning : Learnt the basic concept of 8085 micro processor and acquired detailed knowledge of verilog HDL

PROJECT 3

Title : Design of cordic core and its various applications

Durations : 2 months

Language : Verilog

Synopsis : The project was executed with:

Simulation of the whole project on MOdelsim and acquiring its area,power and timing analysis.

Key learning : Learnt the basic concept cordic algorithm and verification

PROJECT 4

Title : Design and Verification of Memory Module

Tools : Model Sim

Description:

The objective of the project is to design a 1024x8 memory module, write test cases and test automation using Model Sim. The test cases like address test and data test is written and verified.

PROJECT 5

Title : Design and Verification of FIFO

Tools : Modelsim

Description:

The objective of the project is to design a 16x8 FIFO module, write test cases, assertions and test automation using Modelsim. The various test cases were written and integrated with test environment for automated testing , functional and code coverage. The coverage reports were generated and analyzed.

PROJECT 6

PROJECT TITLE : Timing Analysis of RISC CPU Core

Technology : TSMC 65nm

Tools : Modelsim

Description:

. Various synthesis reports were generated and analyzed the area, power.

INDUSTRIAL TRAININGS

Has completed industrial training at Regional Telecom Training Centre Trivandrum,(2010)

BEYOND CURRICULUM

Won the first prize for best short film in college level(2011)

Won 3rd prize for “Green Marketing” in Inter-College Tech Fest held at Federal institute of Science and Technology

Participated in Circuit debugging at College level

Learned Artwork in Glass Painting.

Learned to play organ.

Participated and won third prize in Tableau at Arts Festival ,at College level.

PERSONAL VITAE

Date of Birth : 07/07/1989

Residential Address : POORNAKRIPA,AMPADY THAZHAM LANE,

SREE POORNATHRAYEESA ROAD,

POONITHURA,ERNAKULAM

PIN:682038

Ampadi Thazham Lan Sree Poornathrayeesa Road,

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