Engineer Design

Mohammed Iqbal Gudmal

**** ******** **** **** *** F228

Austin TX-78749

Phone: 214-***-****

Email: ***********@*****.***

Summary

• Masters Degree in Electrical Engineering with 30 months of embedded C programming experience.

• Experience and understanding of Real Time Operation Systems. Experience in developing modules independently, following the development cycles.

• Strong background of computer and parallel architectures.

• Current visa status F-1, Eligible to work on OPT for 29 months. Open to relocation.

Technical Expertise

Simulation Design: Modelsim, Synopsys, Verilog, VHDL

High level languages: C, Basics of C++, Matlab

Scripting: Perl, Shell programming

ASIC CAD tools: Synopsys (Design compiler, Design Analyzer), Cadence Encounter

Physical/Layout: Cadence tools (Analog artist, Virtuoso, Assura, Simvision), Synopsys (HSPICE, Primetime)

Assembly languages: Programming for 8085,8086, and 8051 Microcontoller

Operating Systems: UNIX, Windows 98/NT/XP,

RTOS– ERCOSEK, VxWorks

Software Tools & Packages: IBM Rational Clearcase, Rational Clearquest,

X-MetalAuthor. Codewright, ETAS- INCA, UDE, MISRA, Simplescalar, Win-RTM, Canalyser, CAN2000

Work Experience

ARM-Austin Texas (August 2009- December 2009)

Job title: Patent Intern

• Involved in analysing ARM patents dealing with processor and bus architectures various circuits patents and check if they are implemented in any of the ARM products.

• Involved in patent infringement analysis tasks.

• Updating the information collected in ARM internal Wiki pages

Robert Bosch India Private Limited, Bangalore, India(July 2005-November 2007)

Job title: Senior Software Engineer

• Developed and tested various modules in vehicle functions such as AC, Starter Control and Vehicle Diagnosis. Conversant with embedded system architecture, design methodology, implementation and testing process.

• Developed automated test scripts with Excel and proprietary tool INCA which are used to test the code on Labcars.

• Good comprehension of microprocessors, microcontrollers, usage of communication protocols like CAN and flash programming. Knowledge of device drivers for diesel engines.

• Proficient in the usage of embedded software engineering tools like compilers and debuggers.

• Worked on tools like Canalyser and CAN 2000 used in Vehicle Diagnostics

Education

University of Texas at Dallas (Graduation: May 2010) GPA: 3.4

Master of Science in Electrical Engineering

Vishweshwariah Technological University, Karnataka, India (Graduation: June 2005)

Bachelor of Engineering, Electronics and Communications

Projects

• Scheduling mechanism for Train system – Real time system

Scheduling methodology using vx-works platform for different operation of train system.

• Simulation of Branch Predictors in superscalar processors using the Simplescalar tool

Implemented branch predictors such as Tournament Predictor, (m,n) predictor, innovative predictor such as GSkew

predictor using Simplescalar tool.

• Parallel Architectures and Systems

Implementation of Radix sort, Sample sort algorithms on a virtual shared address machine using threads in C. Matrix

multiplication along with sample and radix sorting using MPI. Topics included parallel programming environment, fine-grain

parallelism such as VLIW in superscalar processors, parallel computing paradigm of shared-memory, distributed-memory.

• Testing and Testable Design

Learnt techniques for detection of failures in digital circuits and systems, fault modeling and detection, functional

testing and algorithms for automatic test pattern generation (ATPG).Tested digital modules such as PLA's,

memory circuits, data path etc using VHDL/Verilog in Synopsys and Tetramax.

• 512 Bit SRAM Custom Design and Layout using IBM 130nm process

Designed with an aspect ratio close to 1. Design aimed at reducing the speed of the RAM read/write cycles and the Area/Bit

of the SRAM

• Mini Stereo Digital Audio Processor

VHDL implementation of this ASIC that performs convolution of audio samples. Implemented based on unique MSDAP

algorithm with coefficients expressed in terms of powers of two.

• First order Linear Interpolator- Full Custom VLSI design

Designed a linear interpolator to maximize the output sample rate. The system received low rate samples in signed 8-bit 2's

complement format and 2-bit rate increase factor R = 1, 2 or 4.

• Two way innovative branch fetching scheme to improve the branch prediction accuracy

Exploring different branch predictors and assessing prediction accuracy confidence level, based on which a bidirectional

fetch mechanism was designed with the help of Simplescalar tool in C language.

Related coursework

• VLSI design

• Advanced VLSI Design

• ASIC Design

• Testing and Testable Design

• Low Power VLSI Design • Computer Architecture

• Advanced Computer Architecture

• Parallel Architecture and Systems

• Real Time Systems

• Analog IC Design

Availability

Immediate. Ready to relocate at my own expense.

References

Available upon request.

Keywords

MSEE MSCE BS 2 years Hardware engineer CMOS MOS chip design system design chip verification circuit design computer architecture ARM Intel architecture Applications engineer entry level experienced C C++ Verilog HDL VHDL HSPICE, Assembly ARM Spectre Cadence Full Custom VLSI Design CAD Real Time Systems (RTOS Embedded System 95, 98, ME, NT, 2000, XP, Vista, UNIX, Linux, Shell, MS DOS, Solaris.

Profiles http://www.linkedin.com/in/iqbalgudmal

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