Engineer Design
Resume:
Ivan Djordjevic
Fountain Hills, AZ 85268
********@*****.***
Computer
Skills
Languages: Matlab, Mathcad, Mathematica, C/C++, Verilog,
VHDL, Tcl/Tk, Python, Lisp
Software: DC, PT, Astro, Magma, LaTeX
Project: PMP
Experience Chipset Architect, Intel Corp., Folsom, CA 2010-2012
Drove requirements, architecture and implementation for an IO processor.
Power performance model for PCH using queueing theory approach and SystemC
(w/TLM).
Exploration into integration of voice and gesture commands into PCH.
Created executable speci cation framefork based on PSL, NuSMV, ACL2.
USB3 C-Spec owner for PCH. Feature set de nition and high level architecture
speci cation.
Silicon/Systems -Architect, Intel Corp., Chandler, AZ 2006-2010
Created a systolic framework within Tensilica processor for performing delay in-
sensitive DSP operations with fully utilized pipeline and single cycle throughput.
This was achieved by using Flix instructions with custom lookup queue formats.
Forward Error Correction (FEC) algorithm development for ATSC, DVB-S2,
DVB-T2, includes TCM (Viterbi, BCJR) and LDPC. Tools used Matlab, Math-
ematica, maxima, C++.
Contributions to architecture de nition for MoCA/DOCSIS SOC consisting of
ARM11MP cores and Sonics infrastructure. Trade o analysis on system per-
formance, SW/HW partitioning, con guration, implementation and die size cost.
Also performed various side tasks, like design of MDIO and SPI Flash controllers,
resolved FPGA timing issues, performed routability study of various hardened
macros of the Sonics switch.
Created On-Chip low latency elastic interconnect. Delivered complete solution:
graphical con guration tool, RTL, circuits, layout and timing closure, character-
ization of the circuits and prototyping in FPGAs. Used Malab and Python for
high level modeling and topology optimization and AMS for low level modeling
of circuits.
Cluster Manager, Intel Corp., Chandler, AZ 2003-2006
Architecture and project leadership of a DSP processor performance improve-
ments activity: achieved doubling of speed performance (from 250MHz to 400MHz)
by pipeline architecture modi cations and achieved 50% area reduction by im-
plementation of e cient cache memory subsystem.
Supervised delivery of audio and IO peripherals blocks, validation, emulation,
FPGA) for a media processor chip. Blocks included a DSP processor, encryption
engine (AES, CSS, C2), high speed IO devices (PCI, SATA, USB), serial devices
(I2S, SPDIF, I2C, AC97, UART, ...). Provided SW/HW partitioning, SW API
and silicon u-architecture for those blocks.
Responsible for architecture, speci cation, project planning and performance
management of a group of engineers. Coordinated multi-site development. De-
ned integration strategy and supervised implementation. Pre- and post-Silicon
bring-up and debug. Used a range of tools, from SignalTap for FPGAs to Quick-
Turn emulators.
Sr. Component Design Engineer, Hudson, MA 2000-2003
Lead a multi-site task force on PD tool
ow and methodology, synthesis taskforce
and functional veri cation taskforce. Challenge was to integrate and educate a
new 20+ person team in an SOC/STD cell design ow.
Lead an exploration into recon gurable xDSL data-pump architecture resulting
in VLIW processor architecture proposal. Participated in ADSL DSP algorithm
development which resulted in new DSP instruction extensions to the ARC in-
struction set (CRC, HPM, MAC instructions).
Created chip level veri cation environment and methodology. Setup cluster level
OCP I/F veri cation environment. ADSL SOC integration, system level infras-
tructure and internal interfaces test bench, embedded DSP C/asm code, system
level AFE interface debug,integration of USB IP. FPGA prototyping with Syn-
plicity
ow. Mentored junior engineers. Interfaced with ASIC vendors regarding
tools and processes.
Architected and implemented N:1 OCP bridge arbiter/dearbiter system, with
multiple arc processors and distributed memory subsystem with multiple time
domains and heterogeneous interfaces,like MCBSP serial interface, ARC-AHB
bus arbitration bridge.
ASIC Design Engineer, Newbridge Networks Corp., Kanata, Ontario 1999-2000
Architected and implemented reference model for a IP route lookup ASIC in
Specman/E environment which was used to verify system level functionality. Set
up a distributed co-simulation environment with SA1200 NT based simulator and
FPGA RTL in Modelsim simulator on Solaris.
Sr. Software Designer, Newbridge Networks Corp., Kanata, Ontario 1996-1999
OC3 ATM NIC device driver design, implementation and maintenance for SGI
IRIX platforms with PCI , GIO, EISA and VME buses. Implemented FIFO
receive mode on Novel OS. Custom software installation program for the Main-
Street Express. Program implemented in iTCL/TK as prototype and then in
C/C++ with RogueWave classes and Motif Widgets libraries on Solaris. Main-
tenance and re-design of the redundancy system with Informix as the database.
Evaluation of third party products for integration in Mainstreet Express or for
integration in the development environment (Silverrun).
Software Developer, Public Sector Systems, Ottawa, Ontario 1993-1996
Custom GUI utilities programs in client-server environment using VB 4 and
SQLWindows, database conversions using C/C++. Telephone and on-site tech-
nical support including installation, optimization and troubles hooting applica-
tions (RIMS) , operating systems (SCO UNIX, NOVEL) and databases (Oracle,
SQLServer, Sybase, SQLBase).
Technical Systems Manager, Yugoslav Bibliography-Information Institute,
Belgrade, Yugoslavia 1989-1993
Daily management of DEC VAX/VMS on ISDN. Designed and coded program
for UDC Index in COBOL using RDB. Application implemented in C and used
probabilistic approach (Markov chains).
Education University of Belgrade, Yugoslavia, 1993, M.Sc. Solid State Physics (no thesis)
University of Belgrade, Yugoslavia, 1987, B.Sc. Chemical Engineering,
Electrochemistry
De La Salle College, Malta 1975-1980
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