Electrical Engineer

XIONG, WENTE

Phone Number 315-***-****

E-mail Address *****@*******.***

Objective: To perform FPGA, Circuit, and VLSI design for a fast-paced, growing company

DESIGN SKILLS

Circuit Design Tools: Synopsys Cadence, Virtuous, SPICE, Orcad, IAR Embedded Workbench

PCB123, LabVIEW

Programming Languages: Verilog, VHDL, C, C++

EXPERIENCE

OPTOGENESIS Inc. Austin, TX

Electrical Engineer (Aug 2011- Current)

Independent Contractor, Electrical Engineer (Dec.2009 - Aug 2011)

Project Brief: Construct a complete home security system including user end devices, server and application software.

Challenges and main tasks:

Seek for the right combination of user end deivces and sensors.

Perform desired application on user end devices through their specific API functions.

Develop circuit model schematic and layout in PCB123.

Update sensor data to an internet server and maintain it with LabVIEW.

Read IR sensor MLX90614 via Arduino board.

Implement Xbee module to allow Zigbee communication between different Arduino nodes.

Implement Ethernet module to allow Arduino node to send sensor data through an IP address.

Receive and update sensor data from/to the server end Pachube.com.

Design the combination circuit of Li-ion battery charging module, laser driver and motor drivers.

Develop circuit model schematic and PCB layout in PCB123.

Implement TMEX functions to control 1 wire devices including A/D converter, I/O relay,

temperature and humidity monitoring, ibutton software encryption in LabVIEW.

Import Zwave devices into LabVIEW using .NET SDK.

Write test plans and debug the whole system.

SYRACUSE UNIVERSITY Syracuse, NY

A FPGA Implementation of Independent Component Analysis Circuit (Sep. 2008-Dec.2008)

Project Brief: Implement Independent Component Analysis Algorithm and its applications of distinguishing components of the mixture sample extracted from water.

Challenges and main tasks:

Define the real-world problem into proper mathematical model.

Implement the mathematical algorithm in Simulink.

Program it onto a FPGA in Xilinx.

Design the circuit to implement the algorithm (Matrix Calculations) in Simulink environment.

Creation of the testbenches in Xilinx for the logical test.

Place and route of FPGA using Xilinx as the final implementation.

Design and Simulation of an Operational Amplifier (Sep. 2008-Dec.2008)

Project Brief: Design an operational amplifier and verify its performance.

Challenges and main tasks:

Choose the desired components after calculation of the intrinsic parameters of the circuit.

Simulation of the operational amplifier circuit properties in Orcad environment.

Design the operational amplifier from 3 parts: amplify stage, intermediate stage and output stage.

Choose the desired components after calculation of the intrinsic parameters of the circuit.

Simulation of the operational amplifier circuit properties in Orcad environment.

Robot Control (Sep.2008-Dec.2008)

Project Brief: Program a robot to outrun other competitors in a robot race.

Challenges and main tasks:

Program the robot via C code in Code Warrior environment.

Improve the original code in searching for the lines, test drive and find optimum scheme.

Program the robot on a Motorola single chip via Code Warrior (NI product) to do all the functions.

The robot detects the obstacle, finds its way around the obstacle and reacquires the line in the

direction to the finish line.

Test drive several times on the track and decide an optimum scheme from the other 2 people's idea in our group.

Improve the scheme before the match and finally win the second place on the track among 6 teams.

8 Bit Microprocessor Chip (Oct. 2007-Dec.2007)

Project Brief: Design an 8 bit microprocessor chip in 0.6um technology in Cadence Virtuous.

Challenges and main tasks:

Physical design on registers and ALU from existing libraries.

Implement Control Unit modulation in Verilog code and verified its function in testbench code.

Floor plan for the registers, ALU and Control unit. Make interconnections between them considering potential heat problem and time delay.

Design an 8 bit microprocessor chip in 0.6um technology in Cadence Virtuous.

Physical design on registers and ALU from existing libraries.

Implement Control Unit modulation in Verilog code and verified its function in testbench code.

Verify chip functionality using Cadence Analog environment.

Floor plan for the registers, ALU and Control unit.

Make interconnections between them considering potential heat problem and time delay.

EDUCATION

Master of Science, Electrical Engineering

Syracuse University Syracuse, NY 2007-2009

Excellent Student Award 2008, 2009

Bachelor of Science, Electrical Engineering,

University of Science and Technology Beijing Beijing,China 2003-2007

Excellent Student Award 2004, 2005

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