Hardware Engineer - Signal Integrity

PENG YE

Tel: (Cell) 850-***-****

Email: ********@*******.***

Professional Summary

Senior Electrical Engineer with MSEE degree and 4+ years hand-on industry experience on electrical hardware design.

 Experienced in circuit design and Signal Integrity analysis

 Experienced in schematic entry, PCB design and layout (Cadence toolset)

 Proficient in various electrical interfaces (design limitation, validation etc)

 Good at design validation and debug, good problem solving skill

 Familiar with many programming languages (C/C++, MATLAB, Perl, VB)

 Team player with good communication skills

 Self-motivated and hard working

Professional Experiences

06/2006 to present Senior Hardware Engineer, Intel Corporation

 Designed Intel microprocessor based server prototypes and products, including Silicon Enabling Platforms, Customer Reference Board and high volume products; Provided feedback to help silicon optimization;

 Created design schematic; defined PCB stack-up; performed PCB placement study and layout study; generated PCB routing rules and review PCB layout to the rules to ensure design quality; review PCB silkscreen and manufacturing documents;

 Performed circuit analysis, timing analysis, noise/EMI analysis, reliability analysis and Signal Integrity simulation, using HSPICE, Cadence PCB SI, and self-coded scripts. Traded off risk, feature, performance and schedule;

 Performed worst case margining analysis and validation on high speed buses; applied DOE method and statistic analysis to predict mean time to failure (MTTF) and failure rate in high volume manufacturing environment;

 Developed validation testing procedure and instruction; used Tektronix Real-Time and Sampling oscilloscope to validate spec compliance; debugged failures;

 Developed work procedures to improve efficiency and productivity; created and updated technical documents and automation scripts for the team;

 Worked closely with customers to address complex designs and concerns; worked closely with Outsource Design Center (located in Shanghai and Taiwan) to ensure designs meet Intel quality requirements;

Advanced Experience in design and validation on various electrical interfaces:

 QPI (6.4GB/s), SAS/SATA (up to 6GB/s), DDR3 (up to 1600MHz), USB2.0 (480MHz), Clock (up to 133MHz), MII/RMII (25MHz/50MHz), PCI (33MHz to 133MHz), SPI (up to 33MHz), JTAG, I2C and Reset interfaces (miscellaneous), and etc.

05/2005 to 06/2006 Signal Integrity Engineer, Stratus Technologies, Inc

 Designed Stratus brand Fault-Tolerance servers based on Intel microprocessor and Altera FPGA;

 Reviewed design schematic and PCB routing; provided Signal Integrity feedback to improve design quality;

 Completed Signal Integrity simulation and worst case analysis on FBDIMM and PCIE (Gen1) using HSPICE, Cadence SPECCTRAQuest SigXplorer, with consideration of ISI, crosstalk and other noises;

 Built via model and connector model for FBDIMM simulation using CST Microwave Studio 3D field solvers;

 Reviewed voltage regular design to improve power efficiency; reviewed decoupling capacitor placement to ensure robust power delivery to all components;

 Worked closely with the external PCB routing service bureaus, interacted with the CAD engineers to route our PCBs correctly.

Education

08/2003 to 05/2005 MS, Electrical Engineering, Signal Integrity

University of South Carolina, Columbia SC

GPA:3.9/4.0

09/1999 to 06/2003 BS, Electrical Engineering, Communication System

Wuhan University, P.R. China

References

Available upon request

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