Verification Engineer

Hemini Shah E-mail: ******.****@*****.***

Contact No.:510-***-****

Summary

• 5+ years of hands on experience in Verification methodology.

• Develop unified verification solution using different methodologies such as Verilog/VHDL, Coverage driven, Assertion based, RVM, AVM etc.

• Expertise in Hardware Verification Language (HVL) like System Verilog, VERA and Hardware Design Language (HDL) like Verilog, VHDL.

• Great expertise in standard ASIC verification flows including Verilog simulators, synthesis, timing analysis & tools.

• Hands on experience on EDA tools like Verilog XL, NC-Verilog, VCS, Modelsim.

• Strong ability to debug design using EDA tools and VCD Viewers like nWave, Simvision, Debussy-Verdi.

• Excellent working experience in Perl, Shell, TCL scripting and Makefile in UNIX Environment.

• Experience in developing verification strategy based on coverage driven or directed test approach.

• Study design and functional specification in detail. Implement and deploy verification test plan and

environment to the Companies Sarnoff NJ, Netstreams TX and Qualcomm CA.

• Experience in measuring code coverage, functional coverage and running gate level simulation.

• Strong programming skills in C/C++

• Working experience in RTL Scripts version control tools like CVS and Design Sync, Bug Tracking System(BTS), Bugzilla, IMS.

• Experience in module level, chip level and SoC level verification.

• Worked on Video signal Simulator, Fame Sync Decommutator Unit and Euro-zig card designing for Space Research Organization.

• Excellent communication skills and profound ability and desire to work in a team environment.

• Strong ability to write detailed verification test plan.

• Experience in using QTP automation tool and VB Scripting for Front End testing on Client-Server and Stand-Alone Application.

• Performed Back End testing by executing SQL Queries.

• Knowledge of Quality Center for testplan and bug tracking.

Technical Skills

Hardware Description Language Verilog HDL, VHDL

Hardware Verification Language SystemVerilog, VERA

Verification Methodology RVM, AVM

EDA Tools Verilog XL, NC-Verilog, VCS, Modelsim, Xillinx Foundation series, SimVision, Nwave, Debussy-Verdi, Altera, Pspice, Matlab

Hardware Architecture x86, 8085, 8051

Programming Language C/C++, Assembly Language Programming (8051, 8085, 8086)

Script Language TCL, Shell Scripting, Perl, Makefile

Operating System Linux, Windows NT/XP, Sun Solaris, Unix

Other Tools CVS, Design Sync, VNC Viewer, VPN, Bugzilla, IMS Bug tracking system

EDA Expertise Behavioral/Architectural Modeling & Logic Synthesis

Technical Knowledge

On Chip Bus Standards AMBA 2.0 Bus Specification, AXI(AMBA 3.0) Bus Specification

Off Chip Bus Interfaces PCI Express, USB OTG, Serial Rapid IO, I2C

Video Standards H264 (MPEG 4 Part 10), MPEG 2

Processor ARM Processor, NIOS, DM642 DSP

Peripherals UART, SPI, I2S, GPIOs,

Professional Experience

NPD Group Port Washington, NY Sep 2009 to Aug 2010

Market Research Application

Market research application manipulate consumer and retailer data, process them, create custom reports which helps client to decide Product Assortment and Line Development, Distribution Planning, Consumer Solutions, Price Optimization, Growth Opportunities, Strategic Planning & Positioning. Market research application has certain stages like PowerWarehouse, DictionaryManager, ExceptionManager, Custom reporting, where all consumer data and retailer data has been sorted out based on selection of region, season, gender etc. these processed data finally displayed on Custom Reporting tool.

Responsibilities

Interacted with Business Analysts, Project Manager, and Developers to get the flow of the Interfaces. Verify couple of automation tools to find best match for company’s application.

Created a Master test plan for functional integration system and user acceptance testing in QC.

Reported bug using Quality Centre and tracked the bug repair status.

Designed, developed and executed QTP VB scripts for functional, regression testing, and callable scripts.

Improved the flexibility of the functional tests by parameterizing the entire test, by inserting checkpoints like Standard check points and Data base check points.

Responsible for creating and enhancing Creating Synchronization values using QuickTestPro(QTP).

Analyzing FS (Functional Specifications) and BRD (Business Requirement Document).

Wrote and executed SQL Queries to retrieve data from Oracle.

Participated in various Cross track meetings and critical path meeting to discuss various risks & “Blocking Go live” issues.

Involved in all phases of testing, Functional, User interface, and System testing, Regression, Performance testing, in various builds of the application.

Environment: QTP, Quality Center, Java, Toad

Qualcomm San Diego, CA Oct 2007 to Aug 2009

Mobile Handset Chip Verification

MSM chipset solutions enable cost-effective mobile handsets with advanced capabilities that leverage 3G technology yet minimize development time. Offered on four discrete platforms for tailored functionality, each chipset is integrated with a select set of features from the multimedia suite of applications to enrich the user experience while maintaining cost-target objectives. Chipset is integrated with a select set of features like multimedia, graphics, interfaces, processors, DSPs, memories, etc. to enrich the user experience while maintaining cost-target objectives. Chip provides very useful user friendly functions, like GPS, Audio, Video, TV, Camera, Gaming, Bluetooth, Connectivity, etc.

Responsibilities

Key person for USB OTG Verification : USB OTG specification allows mobile phones to act as host allowing USB peripherals to be attached. Key person to bring up USB verification environment up and running at SoC level. Verification environment uses Native flow. Create and debug testcases using Vera-C Native Simulation for features like HNP, SRP, USB operations at High and Full Speed, etc. Active member for USB Boot Simulation.

Responsible to verify interrupt service routine from processor to each module at SoC level.

Created test environment to integrate chip using mixed language environment like VERA, C, VHDL using Modelsim and VCS simulators.

Developed testcases and verification environment of such peripherals USB, Secure Digital Card Controller, UART, Stream IF, etc. using chip level environment.

Wrote script for fully automated regression of entire chip.

Used CVS as version control tool to handle verification environment in repository.

Constructed functional coverage group and points to get Functional Coverage.

Reported PR and maintained IMS Bug Tracking.

Contributed in Gate Level testing and Boot simulation.

Environment: Vera, C, VHDL, Verilog, Perl, Shell Script, Assembly Language, Modelsim Simulator, Makefile, Solaris, IMS Bug tracking system, CVS Version Control tool, Debussy-Verdi, VCS

Mobile Station Chip Verification

3G base station chip is most advanced Cell Site Modem up to date and leads the wireless industry in supporting the highest network data rates. This chip used to improve network performance and fast switching. With capacity that provides for up to 256 simultaneous calls on a single chip, it will enable design of new, much smaller and more versatile base station equipment. It includes ARM Processor, QDSPs, Modem, SRIO, Internal and External Memories, peripheral bus, AXI Crossbar, etc.

Responsibilities

Active team member on SoC level integration and verification.

Responsible for Serial Rapid IO Verification: Rapid IO is the main feature of MBS Chip. It is designed specifically for the signal processing, networking, and communications fields. Active member of developing mixed language verification environment consists of SystemVerilog and Vera. Define, develop and debug Assertions on various interfaces like Rapio IO Interface and AXI Interface. Created custom Scoreboard interface not only checking data integrity but also provides bridge between two different language domains.

Key person for On Chip Peripheral Bus Verification: The on-chip peripheral bus (OPB) is designed for easy connection of on-chip peripheral devices. It provides a common design point for various on-chip peripherals. Responsible person of developing re-usable verification environment using RVM Methodology for AHB protocol. Created various verification modules like transactor, collector, scoreboard etc. Created functional coverage points and group.

Used Design sync revision control tool to handle verification environment in repository.

Responsible for developing verification environment and testplan.

Constructed functional coverage group and points to get functional coverage.

Reported PR and maintained IMS Bug Tracking.

Involved in Code coverage and functional coverage Analysis.

Environment: Vera, System Verilog, Modelsim Simulator, Makefile, Shell Scripting, Solaris, IMS Bug tracking system, Design sync Revision Control tool, Debussy-Verdi

Sarnoff Princeton, NJ Oct 2006 to Sep 2007

H264 Verification

The H.264Codec is the digital video codec standard which is noted for very high-rate compression. This core is responsible for doing DCT based integer transform and quantization of motion estimated residuals in H264 standards.

Responsibilities

Responsible for Transform Quantizer Verification: Being one of the most important part of hardware accelerator, this block has interfaces with other blocks, memory and host processor. It is responsible for doing inverse quantization and transformation in case of decoder and/or reconstruction. The block performs the processing on 16*16 or 4*4 macro block.

Responsible for Deblocking filter Verification: The deblocking filter is applied after the inverse transform in the encoder and in the decoder. The filter smoothes block edges, improving the appearance of decoded frames. The filtered image is used for motion-compensated prediction of future frames.

Responsible for developing the test cases as per the test plan. Performed RTL verification. Involved in code coverage analysis.

Developed perl and shell scripts for test automation, regression and code coverage analysis.

Reported PR and maintained Bug Tracking.

Environment: Verilog HDL, VCS Simulator, Shell Scripting, Perl, Linux, Windows XP, Solaris, Bug tracking system CVS, E-Max tool, C, Simvision

NetStreams Austin, TX Jul 2006 to Sep 2006

AVDS (Audio Video Distribution System) Verification

The overall objective of this product is to design single prototype for the AVDS system. The FPGA firmware handles analog or digital audio traffic. AVDS is standalone multi room audio video system. This product also utilized to distribute S-Video and multi channel audio to multiple home theaters. This product has various interfaces like DM642 DSP, CS8416 (SPI), PCM1755 (I2S), UART (RS232), ADC, DAC, etc.

Responsibilities

Key member of a verification team, responsible for implementation of verification environment and generation of high quality test cases.

Functional verification of RTL logic blocks.

Responsible for module level and system level verification.

Defining and developing verification components, protocol checkers and data integrity checkers.

Responsible for verifying all possible data path of design using post-processing scripts.

Measuring code coverage and running gate level simulation to verify the RTL.

Environment: System Verilog, Verilog HDL, Verilog XL, VCS Simulator, Shell Scripting, Perl, Linux, Bug tracking system, CVS

Xilient Cupertino, CA Feb 2006 to Jun 2006

XM-200 SOC Verification

The XM200 is targeted at the networked CE space including the media extender market. The XM200 includes all of the features of the XM100, adds the networking feature set including packetization, link monitoring, error resilience and the QAM modulator. SoC consists of 400MHz 16/32-bit DDR unified memory controller , MPEG-2, Transport stream I/O controller supports up to six base band TS interfaces, I2C, GPIO, PCIE.

Responsibilities

Develop master testplan for unit-level and chip-level environments.

Develop block and system-level test benches and verification environments

Responsible for PCIE verification and integration of Synopsys PCIE IP with XM200 core.

Responsible for developing the test cases as per the test plan. Responsible for verifying Synopsys PCIE IP using Synopsys PCIE VIP.

Experience of generating DAT file through C code using NIOS IDE Tool.

Reported PR and maintained Bug Tracking.

Environment: Verilog HDL, Verilog XL, VCS Simulator, Shell Scripting, Perl, Linux, Windows XP, BTS, CVS, C

E-Infochips Aug 2005 to Jan 2006

AHB2APB Bridge Verification

AHB-APB Bridge is an interface between AHB and APB. This bridge connects the low bandwidth peripherals on APB with the high bandwidth AHB. This bridge is used in almost all typical ARM based systems where low bandwidth peripheral devices are located on APB bus. Core is targeted for family of Xilinx programmable logic devices. It is targeted for SPARTAN, VIRTEX 2 FPGAs

Responsibilities:

Functional verification of RTL logic blocks.

Defining and developing verification environment, test plan, protocol and data integrity checkers.

Responsible for verifying all possible data path of design using post-processing scripts.

Measuring code coverage and running gate level simulation to verify the RTL.

Environment: SystemVerilog, VCS Simulator, Shell Scripting, Perl, Linux, BTS, CVS

E-Infochips Apr 2005 to Jul 2005

Interlace-Deinterlace Core Verification

IP core, which performs for video and image processing applications. This IP design for high performance with optimized power and space requirement. This IP targeted for multimedia applications like digital camera, set-top-boxes, security system and more

Responsibilities:

Responsible for verifying all possible data path of design using post-processing scripts.

Documentation of Test Plan and Verification Environment

Measuring code coverage and running gate level simulation to verify the RTL.

Environment: Verilog HDL, Verilog XL, Shell Scripting, Perl, Linux, BTS, CVS

E-Infochips Jan 2005 to Mar 2005

Inter IC Bus Controller Verification

It is two-wire protocol. This IIC bus controller connected to device by software address. It is serial, 8-bit oriented and bi-directional data transfer protocol.

Responsibilities:

Responsible for verifying all possible data path of design using post-processing scripts.

Documentation of Test Plan and Verification Environment

Measuring code coverage and running gate level simulation to verify the RTL.

Environment: Verilog HDL, Verilog XL, Shell Scripting, Perl, Linux, Bug tracking system CVS, E-Max tool

ISRO Jan 2002 to May 2002

Video signal Simulator, Fame Sync Decommutator Unit and Euro-zig card Designing

It is bidirectional protocol. The circuit generates two sets of signals, which contains front panel offset information. Frame synchronizer and decommutotor unit is one part of ground check out system. Frame sync unit detects sync and decommutator unit converts into user friendly data. Frame synchronizer and decommutotor unit is one part of ground check out system. Frame sync unit detects sync and decommutator unit converts into user friendly data.

Responsibilities:

Responsible for detailed documentation for functional specification, feature list and Designing of Euro-zig and Extender card.

Designing, placement and routing of Euro-zig & extender card using Cadstar 3.0 software.

Environment: Windows, Cadstar 3.0, Orcad

Education

Bachelor in Electronics and Communication Engineering

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