Engineer Six Sigma

Saurabh Puri

*** ***** ******* **, #**** Phone No.: 408-***-****

Milpitas, CA- 95035 Email: ***********@*****.***

Objective:

Seeking a position in Technical marketing role in a company focused on delivering new technologies & products to their customers.

Professional Experience:

Product Engineer, Cisco Systems, Inc., San Jose, CA, 01/2008- Present

• Promoted to Product Engineer Sr. in 2 years and received several CAP (Cisco Achievement Award) awards.

• Successfully productized Cisco’s highest volume products including 10/100/1000 copper & 10G fiber blades. Currently leading team on Cisco’s next generation service module & EARL (Encoded Address recognition logic) cards. Assist engineers with layout, bring-up and debug of prototypes, qualification & release to production.

• Conduct Root Cause Analysis on reported failures for Catalyst switches at board & chip level. Drive results through the appropriate teams in Cisco to prevent future occurrences & correct fixes released to customers.

• Promote cost savings & quality improvement by working with GSM on new component qualifications.

• Facilitate resolution of all technical issues using available resources including documentation, hardware, software & engineering resources.

• Lead and review Cisco’s New Product Introduction documents for Catalyst 6000 series family.

• Proficient in executive level to detailed technical presentations.

• Mentor & train teams at CM site to ensure they receive the required level of product training.

• Drove savings of more than 1.2 million dollar per year by working with fab vendors on panelization, utilization & fab material.

• Led baseline testing initiative aimed to improve quality of products. Developed & implemented test plans to test for the worst case in production, manage resources, provide technical support to the CM, analyze data & communicate results to management at Cisco.

• Achieved six sigma yields by successfully implementing DFx activities. Ensured that issues related to quality, cost & manufacturing cycle time are addressed early in the life of a product.

• Manage extended teams and possess deep understanding of Signal Integrity, Mechanicals & Thermals. Expertise in BOMs, Component qualification, Stackups and Layout.

Hardware Engineer, Adtran Inc., Mountain View, CA, 01/2007- 01/2008

Re-designed & tested cost reduction T1/E1 & 8 port 10/100 cards leading to savings of $400K per year.

Performed failure analysis on released hardware for critical manufacturing and field issues.

Worked extensively on bring up and debugging of prototype cards that includes switch cards, Gigabit line cards & SONET/SDH cards.

Participated in future design, hardware specifications & test plan reviews.

Developed system & board level tests and test procedures to ensure that the product meets the engineering requirements.

Skills:

EDA/CAD tools : Cadence/Virtuoso, View Logic, Valor, Allegro, SPICE

Programming Languages : Verilog, C

Other tools/skills : Analog, Xilinx ISE web pack, oscilloscope, logic analyzer

Education:

M.S. Degree in Electrical Engineering, San Jose State University, CA, December 2007

Overall GPA: 3.52/4.0

B.Tech Degree in Electronics & Communication, Kurukshetra University, India, July 2005

Overall GPA: 3.8/4.0

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