Engineer Engineering

YORICK WAHAUS

**** ** ********** *** 541-***-****

Corvallis, OR 97330 ******.******@*****.***

http://www.linkedin.com/pub/yorick-wahaus/b/758/967

SUMMARY

Eleven years of engineering experience including yield, visual inspection, defect reduction,

CMP/grind process engineering, and environmental engineering. Engineering owner of visual

inspection tools, review tools, SEMs, CMP tools and Abatement tools. Collaborated with

engineering partners in Singapore to ensure our processes were converged. Lead and performed

multiple defect reduction projects on various products. Evaluated SEM’s and inspection tools for

purchase. Determined and rolled out best system to document the defect learning’s of the fab and

make them accessible fab-wide. Participated in multiple Klarity beta tests, using the beta version

software, documenting problems and participating in weekly review meetings. Developed, tested,

implemented & documented multiple grind and CMP processes for various products during

development

• • •

Klarity Defect Expert Experienced in JMP Proficient in MS Office

• • •

Applied Statistical MEMs Processing Mentored Technicians

Process Control (SPC)

PROFESSIONAL EXPERIENCE

Hewlett-Packard Company, Corvallis, Oregon 2001 – 2012

HP is a technology company that explores how technology and services can help people and

companies address their problems and challenges, and realize their possibilities, aspirations and

dreams.

CMP/Grind Process Engineer 2009 - 2012

Responsible for ensuring CMP/Grind is qualified and characterized to process TIJ, PIJ and

Richter.

• Performed characterization study of SU8 at CMP as a member of the 2LM SU8 process

characterization team.

• Developed CMP/Grind process for Richter (MEMs Sensor).

• Consolidated CMP portion of the CMP/Grind work center into Fab-22 without any interruption

to production.

• Mentored technician to takeover day to day engineering responsibilities for TIJ process.

Environmental Engineer for TDO 2011 – 2012

Maintain engineering models of VOC's, PFC's NH3 and Lead for the TDO fabs. Use models to

determine abatement needs for various process tools. Provide engineering support for abatement

tools.

Visual Analysis Yield Engineer 2007 – 2009

Was responsible for ensuring visual SU8 yield goals were met by monitoring and reacting to SU8

visual and electrical defects.

• Assisted barrier engineering to determine root cause of various SU8 defects

Defect Analysis/AIT Engineer 2001 – 2007

Responsible for ensuring the AIT’s were qualified and characterized to inspect TIJ and Richter.

Responsible to monitor AIT defect rate for Fabs-21 & 22.

• Set-up automated on-line defect reports for multiple inspection steps.

• Launched and participated in multiple defect reduction efforts and excursions for the back end

of line.

• Planned and executed AIT strategy due to fab-21 consolidation with minimal impact to

production.

• Enabled AIT-XP to be used as a yield screen for resistor area defects.

EDUCATION

Master of Science, Chemical Engineering,

Integrated Minor: Emphasizing thin film silicon processing

Project: Empirical correlation of spin coating Newtonian fluids on silicon wafers.

Oregon State University, Corvallis, Oregon

Bachelor of Science, Chemical Engineering,

Materials Engineering Option

Oregon State University, Corvallis, Oregon

PROFESSIONAL DEVELOPMENT

Attended the Lehigh Microscopy School in 2003

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