Analog/Mixed Signal Design Engineer

BINIT JAISWAL

*** * ** ****** **** *********@*****.***

Sunnyvale, CA-94086 USA 469-***-****

Objective – To obtain challenging position as an Electrical Engineer to contribute knowledge of Analog and Mixed Signal Integrated Circuit Design to deliver high quality commitment with self-motivation and dedication

Education

M.S. in Electrical Engineering May 2011

Southern Methodist University, Dallas, TX Cumulative GPA: 3.2/4.0

Bachelor of Electrical Engineering May 2008

Veer Narmad South Gujarat University, Surat, India

Technical Skills

Software: Cadence Design Suite, Spice, Verilog, JAVA, MATLAB, PLC, Dreamweaver, Adobe Photoshop CS4, Paint.Net

Design Ability: Ring and LC VCO, Cristal Oscillator, Charge pump, PLL, DLL, Clock and Data Recovery, Fractional N-Synthesizer, Divider, Band-gap Reference Circuit, Low Noise Amplifier, Broadband Amplifier, High Speed custom CMOS, LVDS, CML Logic, SerDes, Equilizer, Current Mirrors, SRAM, Digital Blocks, PCB Design, SoC Design.

Technologies and Networking Skills: CDMA, GSM, GPRS, EDGE, UMTS, LTE, LAN, WAN, ATM, VLAN, TCP/IP, TCP, UDP, RTP/RTCP, BGP, HTTP, FTP, SS7, IEEE 802.5, 802.11, STP, DNS, SMTP, DHCP, IMS, VOIP, SIP

Application: Microsoft Office (word, excel, power point), Open Office 3.1

Completed certified course in programmable logic controller (Allen Bradley)

Projects

Phase Locked Loop Design. (Technology: TSMC 0.25um)

Design of divide by 32 PLL with supply voltage 2.5V, output frequency 1.28 GHz, phase noise less than -90dbC/Hz and lock time of 1.5us.

Two Stage High Gain Op-Amp Design. (Technology: TSMC 0.25um)

A differential input and single-ended output Op-Amp with 1500 differential mode gain, 0.1 common mode gain, 1.4V output swing and maximum BW.

Limiting Amplifier for SONET Receivers. (Technology: TSMC 0. 13um)

Design Limiting Amplifier with 3 GHz BW and 32dB gain for SONET OC-48 application

Gigabit 16 x16 Crossbar Switch Design. (Technology: TSMC 0.25um)

Crossbars switch with 1 Gbps Data rate, 1 ns Latency, 50% duty cycle and, 16 input-output ports. Also design Physical layout with minimum area using cadence simulator and verify DRC, LVS.

1:2 DeSerilizer Design (Technology: TSMC 0.13um)

Design 1:2 DeMux with 10Gbps data rate and, output swing 0.4V.

Technical Paper

Submitted technical paper to SOCC 2011 Conference on “Extension of Universal Correlation Equation”

Relevant Courses

Semiconductor Devices and Circuits, Transistor Integrated Circuits, VLSI Design and Lab, Advanced Topics in VLSI Design, High Speed Communication Circuits, Data Communication, Digital Signal Processing, Digital Control System

Job Experience

Analog/Mixed Signal Design Engineer at Omni Vision, Santa Clara, CA Sept 11 - Present

Design, development and characterization of embedded analog circuits, such as high speed I/O, SerDes, CDR,

PLL. Design, layout and debug of high speed (multi GHz) circuits

Project Employee at Glow networks, Richardson, TX Aug 11 – Sept 11

RF Signal Measurement (Push to Talk (Qchat) Technology), Cluster Testing, Processing Data.

Quality Control Engineer at Polycab Pvt. Ltd., Halol, India Apr 09 - Jul 09

Perform electrical tests as per IS-7098 and IEC-60502 of cable.

Work as troubleshooter, Apply engineering judgments and make technical decision to solve the faults at site.

Communicate with clients and management throughout testing.

Lecturer in Electrical Engineering Dept. at RMS Polytechnic, Vadodara, India Aug 08 - Apr 09

Conduct academic evaluation course pack preparation, assist in research projects, and perform experiments.

Interact with Industry for organizing guest lectures, seminars and individual visits

Honors

Webmaster, IEEE at SMU

Student Employee of the year 2011, SMU

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