Project Entry

CURRICULUM VITAE

T.VENKATA DIVYA ,

D no:*-*-**3(A),

LAWYERPET, Ongole-523001, Email:********@*****.***

Prakasam Dist, Andhrapradesh. Mobile.No: 809-***-****

Career Objective:

To be placed in a challenging organization that gives me scope to update my knowledge & skills in accordance with the latest trends and be a part of team that dynamically works towards growth of organization.

Educational Qualifications:

Examination Board&University Specialisation /Branch Year of Passing Percentage of Marks

B.E JNT University Electronics&Communication 2010 58%

Intermediate Board of Intermediate Education M.P.C 2006 77%

S.S.C Board of Secondary Education 2004 80%

Operating Systems : Windows XP

Languages : C, Java

OtherSkills : Hardware,Autocad(2D,3D)

• Ability to quickly grasp technical aspects and willingness to learn.

• Adapt to changes.

• Listening and Communication skills.

Strengths:

• Teamwork and leadership Qualities.

• Hard work and dedication to work.

• Cope-Up with any kind of environment.

Achievements:

• I participated one National level paper presentation at St.Ann’s College Of Engineering &Technology in Chirala.

• I have done Real Time Project in my final semester.

About Project:

Project Title :A Low Power Fast Counting Bloom Filter

Language : VLSI

Description : An increasing number of architectural techniques have relied on hardware counting bloom filters (CBFs) to improve upon the energy, delay, and complexity of various processor structures. CBFs improve the energy and speed of membership tests by maintaining an imprecise and compact representation of a large set to be searched. This paper studies the energy, delay, and area characteristics of two implementations for CBFs using full custom layouts in a commercial 0.13- m fabrication technology. One implementation, S-CBF, uses an SRAM array of counts and a shared up/down counter. Our proposed implementation, L-CBF, utilizes an array of up/down linear feedback shift registers and local zero detectors. Circuit simulations show that for a 1 K-entry CBF with a 15-bit count per entry, L-CBF compared to S-CBF is 3.7 or 1.6 faster and requires 2.3 or 1.4 less energy depending on the operation. Additionally, this paper presents analytical energy and delay models for L-CBF. These models can estimate energy and delay of various CBF organizations during architectural level explorations when a physical level implementation is not available. Our results demonstrate that for a variety of L-CBF organizations, the estimations by analytical models are within 5% and 10% of Specter simulation results for delay and energy, respectively.

Personal Details:

Name : T.Venkata Divya

Father’s Name : T.A.Krishna Murthy

Date of Birth : 19-08-1989

Martial Status : Single

Nationality : Indian

Address : D no:7-5-113(A),

Near Ayyappa Swamy Temple,

Lawyerpet,

Ongole-523001,

Prakasam (Dist), A.P.

Phone No : +91-809*******

I hereby declare the above furnished information is true to the best of my knowledge and belief. (T.Venkata Divya

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