Project Design
Resume:
Anand T
Address:
Muneshwara Block,
Bangalore, Email:********@*****.***
PIN: 560026 Ph: +919*********
Objective
Intend to work in an environment that enhances my skills and motivates me to utilize my potential to the fullest extent to contribute to the company both individually as well as a team.
Work Experience
Worked as an INTERN in UTL Technologies from September 2011 - July 2012. (M tech project)
Project: Developed an IP core for STM-1 Framer and De-Framer.
Platform: Verilog HDL + Xilinx ISE 13.2 + Cadence + Spartan 6 FPGA.
Technical Skills:
Good Understanding of Fundamentals of CMOS and Digital Design Concepts
Programming Languages: C and Linux Programming, Basics of C++, Verilog, SystemVerilog
Scripting: TICKLE SCRIPTING
EDA Tools: Cadence Virtuoso, Cadence NcSim, RTL Compiler, SOC Encounter
Simulation Tools: ModelSim, QuestaSim
Synthesis and Implementation Tools: Xilinx ISE 13.2, Quartus 11.1
IDE: KEIL
Operating Systems: Windows, Linux.
Project Work
1. “Reconfigurable Controller for a Fighter Aircraft”. (BE Project)
Description: The main objective is to develop a reconfiguration scheme that is reliable and offers a degree of assured success for the targeted types of failure. The reconfiguration scheme is expected to stabilize the aircraft in the event of a control surface failure and provide reasonable command-tracking performance.
2. “Design of CMOS Synchronous 8-bit counter in 45nm CMOS Technology”
(M.Tech 2nd Semester Project). Software requirements – Cadence Virtuoso.
Description: Designed an 8 bit synchronous counter using Cadence Virtuoso and layout using Cadence Layout XL. The GDSII file was extracted for the same.
3. “Design and VLSI implementation of STM-1 Framer and De-Framer” (M.Tech Final Year Project).
Software requirements – Xilinx ISE 13.1, Cadence. Language-Verilog.
Description: Developed an IP core for STM-1, which is the basic unit of framing in Synchronous Digital Hierarchy. The functional verification was done implementing on Spartan 6 FPGA to verify the output. The synthesis and timing analysis of the design was done using Cadence RTL Compiler. The Layout for the same was generated using SOC Encounter and post layout timing analysis was done to meet the timing requirements. The GDSII file has been generated for the same.
Academic Records
EDUCATION Institution Board Year of Passing Marks M. Tech
in VLSI Design and Embedded Systems
VTU Extn. Centre, UTL Technologies Pvt. Ltd, Bangalore.
VTU
Belgaum
2012
74.3
B.E
in Telecommunication Engineering
Acharya Pata Shala college of engineering,
Bangalore. VTU
Belgaum
2008 64.1
PUC
PES PU College,
Bangalore. Karnataka PU Board 2004 74.33
SSLC BHS, Bangalore. Karnataka SSLC board 2002 77.12
Personal Details
Name: Anand T
Date of birth: 08/08/1986
Sex: Male
Father’s name: Thibbaiah
Nationality: Indian
Strengths
• Target oriented.
• Hardworking & enthusiastic.
• Learner at all times.
• Good Team Worker.
Contact this candidate