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Electrical Design

Location:
Sacramento, CA, 95825
Salary:
$30
Posted:
December 06, 2011

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Resume:

Ankit Jain

****, ********** ******, ********* # **, Sacramento, CA 95825 ● 916-***-**** ● pjvxxq@r.postjobfree.com

Objective: Seeking full-time position in the field of ASIC/VLSI Design, Validation, Verification.

Education

Master of Science, Electrical and Electronics Engineering,

California State University, Sacramento, CA Expected Graduation: December 2011 GPA 3.6

Bachelor of Science, Electrical and Electronics Engineering

Saurashtra University, India June 2008 GPA 3.8

Technical Skills

Languages: Verilog, VHDL, C, C++, Assembly

Scripting Languages: Perl, TCL

Operating Systems/Platforms: UNIX, Windows XP/Vista/7

Equipment: Logic Analyzer, Function Generator

Tools/Simulators: Modelsim, Synopsys VCS, Synopsys Design Vision, Primetime, PSPICE,

Xilinx ISE, Matlab, Microwind, L-Edit, AutoCAD, VIM Text Editor

Academic Projects

Pipelined Vector Multiplier and Verification

Performed multiplication between two 64-element vectors, element by element, and stored the product in another vector using 32-bit single precision floating point numbers expressed in IEEE 754 format using Verilog HDL.

Performed pipelining to fetch, multiply and store the data. Used Synopsis tool to synthesize the code and then performed the Verification of the design.

Digital Standard Cell Library

Designed and laid out Digital Standard Cell Library in 90nm CMOS using ‘Microwind’ layout and simulation tool. Developed back-end-design and area optimized layouts for mask creation and simulated using cmos90n.rul technology.

Calculated rise-time, fall-time and delay-time for different values of capacitance and different cases of MOS switching

PCI Card and Cache Logic

Designed two 32 bit PCI compliant devices to perform memory read and write transaction between them. The read transaction should be retried first and performed after write operation to read the correct data.

Made the design in Verilog HDL with the given Arbitration Logic and then performed data transactions with cache memory management.

PCI Express Card Model

Designed transaction layer and data link layer for transmitter and receiver of PCI Express card to perform non-posted memory write transaction between two devices using Verilog HDL.

Implemented the concept of ACK/NAK protocol to confirm the reception of the packets and resend the packets if required.

Advanced Timing Analysis

Designed TCL script to set constraints such as operating condition area, delay time, rise time and fall time for the several combinational and sequential designs and synthesized them using characterization technique and technology library lsi10K.

Verified Timing reports, delays, clock skew, clock latency, clock gating of designs using Synopsis Prime Time tool

Analyzed timing constraints like setup time, hold time, data arrival time, require time for several paths and learned different RTL optimization techniques.

Advanced Access System

Designed and implemented a prototype automatic identity authentication system which is called ‘Advanced Access System’ that uses magnetic card reader to authenticate the identity of an individual

Implemented I2C Protocol to read or write multiple bytes to EEPROM

Used sensor module to make attendance and implemented hardware having P89V51RD2, Microcontroller, LCD, EEPROM, IC MAX 232, RS 232, Keyboard, RTC

Used Topview Simulator for Assembly Language Programming; Keil Software for C programming; Protel DXP for schematics; Flash Magic Software, Hyper Terminal, Docklight Tool for testing

Microprocessor Data path and Control in Verilog HDL

Implemented the concept of microprocessor using Xilinx ISE 10.0 which performs a particular function

ADC and Logic Analyzer in VHDL

Applied an analog input with a variable resistor (potentiometer) to the ADC which caused ADC to generate 8 bit digital output and displayed it on LEDs

32-bit ALU and Verification

Designed a 32-bit ALU which can perform signed logical and arithmetic manipulations; implemented overflow, negative and zero flags in Verilog HDL and performed Verification using Synopsys.

Related Course Work

● Digital Integrated Circuit Design ● Advanced Topics in Logic Design

● PCI System Architecture ● Static Timing Analysis

● PCI Express System Architecture ● Hierarchical Digital Design Methodology

● Micro-processors & Interfacing ● Numerical Analysis

● Micro-controllers & Application ● Advanced VLSI Design For Test

● Microwave Engineering ● Microwave Transistor Amplifiers: Analysis and

● Wireless Communications Design

Work Experience

Student Assistant, University Union, Sac State April 2010 to April 2011

Worked for on-campus job as a student assistant, includes working with Event Services and setting up the meeting rooms for conferences or lectures. Also assisting customers upon their requests.

Electrical and Electronics Engineer, MBH Pumps Pvt. Ltd., India Feb. 2009 to July 2009

Monitored and controlled pressure, temperature, efficiency and electrical ratings of electrical pumps.

Worked with designing and manufacturing departments to ensure consistent quality and coordinated effort.

Lecturer, Government Polytechnic, Ahmedabad, India Oct. 2008 to Feb. 2009

Designed and conducted lessons in major subject areas: Engineering Mathematics and Digital Electronics.

Attended professional growth seminars and workshops.

Hardware Design Intern, MCBS Pvt. Ltd., India Jan. 2008 to May 2008

Designed and implemented a prototype automatic identity authentication system which is called ‘Advanced Access System’ that uses magnetic card reader to authenticate the identity of an individual

Related Seminars, Paper Presentations and Certification

Presented a seminar on Spintronics

Presented a paper on Plasmonics

Participated in industry training for Personality Development, Communication Skills, Leadership skills and Language & Presentation skills.



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