Engineer Test

TIM EBRAHIMY

P.O. Box **** Capitola, CA *****

831-***-**** pegex2@r.postjobfree.com

SR. NEW PRODUCT/DEVELOPMENT ENGINEER

RF, Mixed Signal ~ Digital/Analog ~ Hardware/Software ~ Engineering/Management

Over 10 years experience in all phases of product, test and quality/reliability engineering using various analog/digital measurement instrumentation and ATE, Verigy 93K, Credence Quartet, Teradyne Catalyst plus standalone test systems to test RF CDMA, GSM, WCDMA, xDSL, Ethernet/Fiber Channel, SONET, mixed signal and analog embedded SOC chips and systems, Wireless embedded ARM microcontrollers, FPGA and open systems, hardware and test software development from design phase to full production cycles, full characterization, correlation and qualification, packaging, ATE platform selection with extensive experience in successfully bridging cross discipline activities and people, superb customer and vendor relations, design and implementation of test software, yield enhancement, test time reductions of CHO (CMOS Harmonic Oscillators), memory and RF circuits, analog audio, video, graphics, and high speed Leading telecommunications products with multi-tier-server/embedded ARM processor SOC architecture that encompass Gigabit Ethernet Adaptors, Graphics engines and audio, and video cores, USB, PCIe, PXIe, high speed signal integrity analysis/design for RF and SERDES LVDS multi-layer (thick) PCB design, layout and fabrication.

Core Competencies:

Test and Product Qualification and Characterization utilizing various test systems,, team leadership and hands on participation in all phases of chip and systems development.

Test Data Analysis, Wafer Probing, Flip Chip, On-Wafer Packaging, QFNs, TQFPs, etc. Complex Packaging project team coordination/leadership.

Test Hardware Design and ATE Test Programming to successful productization

Troubleshooting and Problem-Solving until satisfactory results were achieved

New Product Test Development(NPI), Conception to Design/Specification, using Perl scripting, Unix/Linux scripts for test data manipulation and test automation, Yield Improvement, Characterization, and Full Production Releases

Successful Cross-Function Relations Bridging, Vendor Qualification, Project Management, Leading Development Projects and Team Management.

Customer and vendor qualification, continuous interaction to close loopholes, resolving production related issues

Full product transfer to full production to local and overseas test facilities with repeatability and accuracy analysis

Lead role in all test and product engineering equipment qualification (i.e., ATE testers, wafer probers, test handlers)

Provided leadership in innovative packaging options research and development efforts in materials characteristics and affects on analog circuitry

TECHNICAL SKILLS:

Languages

Unix/Linux scripting languages

C/C++

Perl Scripting

LabView

Shell Scripting

ATE Test Languages

Tools

Teradyne Catalyst

Teradyne J750

Agilent 83K

Eagle ETS-300

Credence Quartet

Credence Diamond Series

HP 84K

Advantest Mixed Signal

RF Testers

Other

Oscilloscopes

Signal Synthesizers

Spectrum Analyzers

KVD Analog Tester

Network Analyzers

Waveform Generators

Test/FAB Process Equipment

Statistical DOE Analysis/Yield Improvement Techniques

PROFESSIONAL EXPERIENCE:

MICROWAVE/RF TEST SYSTEMS PRODUCT ENGINEER, CONTRACT WORK June 2009 – Present

Responsible for new product introduction of Microwave and RF test systems programming, Perl and Linux scripting, qualification testing, reliability testing, failure analysis of various devices on ATE and lab. RF and Microwave systems/Instruments testing and NPI (New Products Introduction) process testing, characterization, packaging, design and development of test and qualification hardware, ATE handler/prober platform selection, test process automation, package design and selection, assembly, testing and failure analysis, extensive vendor relations, test platform selection and management, product yield enhancement, and complete overseas transfer of test programs and test hardware at various locations throughout USA.

SENIOR PRODUCT/TEST ENGINEER, Mobius Micro Systems, Sunnyvale, CA Nov 2008 – Jun 2009

Responsible for lab testing, device qualification, ATE testing, characterization, packaging, design and development of test programming debug, Perl scripts, qualification hardware design, ATE handler/prober platform qualification and selection, package design/selection, assembly, testing and failure analysis, extensive vendor relations, platform selection and vendor management, product yield enhancement, and complete overseas transfer of test hardware and software.

Tester-to-lab and tester-to-tester correlation and repeatability analysis. DOE for various techniques and application of new materials and packaging options to improve performance and yields for oscillators and timing devices.

Reason for leaving: To start my own tech consulting firm.

PROFESSIONAL EXPERIENCE:

SENIOR PRODUCT ENGINEER, NetXen Inc., Cupertino, CA Sep 2007 – Nov 2008

Worked with NetXen's Intelligent NIC network I/O processors at multi-gigabit and 10 Gigabit speeds. Responsible for all phases of multi-port 10 Gigabit Ethernet PCIe 2.0 Intelligent NIC products debug, Perl/Unix scripting and development including full qualification of product family of 24 port and 48 port dual 1GbE and 10GbE Ethernet switches provide an optimal solution for in-rack server connectivity. Connectivity solution providing cost-effective copper interconnect with the flexibility of also using optical interconnect with the same infrastructure.

Lab testing, tester-to-tester and tester-to-lab correlations, characterization, yield enhancement, system level testing, software/hardware failure root cause analysis, and complete transfer to manufacturing. Worked with the design, marketing/sales, and manufacturing teams to enhance testing and transfer to manufacturing in a timely manner.

Reason for leaving: Company sold and consolidated staff.

PRINCIPAL PRODUCT AND TEST ENGINEER, PortalPlayer, San Jose, CA Feb 2005 – Apr 2007

Developed from design concept to production phase the COT model product lines (RF, mixed-signal, and digital products). Managed and engineered entire projects. Hands-on ATE test code generation and usage of ATE test programs, oversaw design, simulation and vector conversions, product full qualification, packaging issues, vendor qualification and site auditing, test house activities, and qualifications and test program outsourcing. Fully responsible for the successful bring-up of several new products to market in an orderly and on time fashion.

Designed and developed core components of ATE load boards and sockets and packages for next generation MP3, CDMA, WCDMA and GSM, voiceband/audioband codecs. Implemented various open standards for documentation, application notes and procedures 802.11b, JEDEC standards, and qualification procedures. Led a team of 20 staff engineers. Cross-communicated, coordinated, and parallel developed with five other component developing teams. Enabled company to enter digital media player device markets two years ahead of industrial rivals.

Improved testing and characterization processes specified and designed new methods and integrated into existing lab and production environments. Produced design documents, specifications, and project plans. Managed all task developers on site and abroad to complete projects on time.

Reason for leaving: Company sold and consolidated staff.

PRODUCT DEVELOPMENT ENGINEERING, Consultant Contract Positions, Various Companies, CA Sep 2003 – Feb 2005

Worked as a test/product engineering contract consultant for FABLESS semiconductor design companies to help bring up new pre-production devices to full production either in local or overseas test houses. Qualified, characterized, packaged, debugged, and converted test programs. Worked with outside vendors to build load boards, test sockets, probe cards, qualify, characterize, and enhance yields for high resolution mixed-signal voice band devices used in mobile communications on Teradyne Catalyst and Credence Quartet ATE machines.

Tested, developed, and characterized multi-chip packages silicon substrate interconnects quad high-speed S-Ram memory modules. Heavy interfacing with wafer processing, packaging, qualification, substrate processing, load board, and probe card designs. Improved yield from 60% to 98% by identifying root cause of wafer and package anomaly, characterization of packages and material, qualified products, and implemented better test coverage in the test patterns. Wrote and converted wafer sort and final package. Tested programs for high-speed memory ICs. Devised new test techniques, test scripts using perl and moved automated test platform to higher speed Teradyne Catalyst ATE from PCB board tester.

SENIOR STAFF SYSTEMS ENGINEER, Advantest America, Inc., Santa Clara, CA Jan 1999 – Sep 2003

ATE systems level OS (operating systems), software and hardware applications and development for testing of digital, mixed-signal codecs, DAC/ADC converters, SOC modules, RF cellular CDMA, WCDMA two and three stage Power Amplifiers (PA), embedded memory, CPU, baseband, high speed chips and systems, and LCD drivers. Technical pre- and post-sales support, customer interfacing, technical presentations, held technical seminars and customer training, customer site visits, technical support in software and hardware test development, product demonstrations, show coordination, ATE operating systems debug, hardware and test program debug and generation, and applications engineering support.

Led team of 12 sales and applications engineers to improve new ATE design and implement new automated system enabling customers worldwide to improve and simplify hardware and software development using Advantest Systems, support via telephone, fax, email, and the internet. Response time to customer requests reduced from days to minutes. Efficient reporting resulted in faster troubleshooting, bug resolution, fewer staff involvements, and higher customer satisfaction.

PRODUCT/TEST ENGINEERING MANAGER, Datapath Systems, Inc., Los Gatos, CA Mar 1997 – Jan 1999

Led a team of eight Product and Test Engineers in engineering leadership and critique during device design review stage, product qualification, pre- and post-testing, and ESD/Latch-up bench testing. Generated device productization procedures, performed yield analysis, and enhanced yields dramatically through use of statistical methods. Developed test and product specifications documentation. Performed characterization tests and developed test program on HP94000 and Teradyne Catalyst mixed-signal testers. Device characterization, test repeatability analysis, product yield enhancement data analysis, and failure analysis. QA procedures for various ADSL modems and Read Channel devices using UNIX, C, and PC based statistical engineering analytical applications software.

Led the product, quality, and reliability engineering function with responsibilities including sales and customer interface, product introduction, product quality, and reliability engineering.

Acted as the main interface with design, process, manufacturing, test, and quality as product advanced through production and release.

Utilized knowledge about IP selection and integration including complex I/Os, SRAM, SERDES, embedded processors such as ARM, and other IP. Used thorough understanding of test methodology including BIST, JTAG, memory redundancy, and repair.

Related this to test coverage to quantify in terms of escape rate. Responsible for executing ongoing product and process reliability monitoring which accurately represented expected part performance in the field.

Provided customer support through failure analysis and corrective action on RMA’s.

Accountable for probe, die sort, and test yields improvement and monitoring.

Identified and drove programs leading to yield improvement and best in class performance levels.

Provided probe, sort, test yield, and reliability analysis reports and trends.

Reason for leaving? Company sold and consolidated staff.

Product/Test Engineer, TriQuent Semiconductors, Hillsboro, Oregon Feb 1991 – Mar 1997

Responsible for design reviews, fabrication, full test development, characterization, qualification, GR&R studies, wafer PCM monitoring, yield enhancement and correlation of GaAs RF CDMA, WCDMA, TDMA and GSM Power Amplifiers (PA), Up/Down Converters, Switches, Mixers and Receiver chipsets. Worked with designers, program managers, customers, process and fabrication engineers to produce reliable, RF Compound Semiconductor ICs that meet specific electrical performance requirements. Developed process flows and design elements to achieve required circuit performance. Designed and monitored in-line, DC and RF probe test functions, structures and test results. Collected, analyzed and used characterization data to improve yields. Identify, analyze, and resolve yield and performance limiting factors by identifying root causes and implementing improvements. Assisted and/or lead new product/process development and failure analysis. Review circuit layouts for manufacturability and design rule compliance. Defined part-specific process flows.

EDUCATION:

Bachelor of Science, Post Bachelor course work toward Master of Science in Electrical Engineering

Boston University/ Boston, MA

REFERENCES:

References are available upon request.

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