suhcitra_resume

SUCHITRA ************@*****.*** Mobile: +91-991******* Bangalore

+91-984*******

Summary

• Seeking opportunity in the field of Hardware Verification in a competitive work environment and achieve a challenging and responsible position.

• Good exposure to Verilog, System Verilog test bench creation, analysis and waveform debugging, Assertions, VMM and basics of OVM

• Provided onsite customer support on Assertions, System Verilog.

• Well built knowledge of test methodologies and concepts

• Strong interpersonal skills and excellent communication.

Professional Summary

EInfo Chip (Feb 8 to till date)

Synopsys India. Bangalore (Client) (Mar 1 to till date)

Verification Engineer

• Product validation for low power and MX for VCS 2012 release.

• Migration of Legacy based testcases and testbench to System Verilog environment.

• Converted the test case of Verilog module to VHDL for NLP(native low power) MX_designs with partial compilation of VCS.

• Filed record number of bugs in limited time.

CVC Pvt. Ltd, Bangalore (Design & Verification Consultant)

ASIC Verification Engineer (Nov 10 to Dec 11)

APB 3.0: VIP migration of existing SV based testbench to VMM testbench

Description:

• Transaction Based Verification of Master DUT of Advanced Peripheral Bus. Completely developed a VMM testbench environment. Successfully created test cases using directed and constraint randomization to verify functionality and added Cover group to measure Functional Coverage.

• Tools used: VCS, Riviera-Pro.

HVL: VMM

APB 2.0: VIP development of APB 2.0 in system verilog.

• Responsible for building the verification environment for APB 2.0

• Used constraint randomization and SV assertions.

• Analyzed coverage gaps and developed strategies to fill coverage holes.

• Tools used: VCS, Riviera-Pro.

Skill Matrix

Hardware verification languages: Verilog, System Verilog

Verification Methodology : Verification Methodology Manual(VMM)

Hardware tools : Riviera-Pro, VCS, ModelSim, Questa, Xilinx ISE

High Level Language : C programming.

Protocols : AMBA APB

Operating System : UNIX, Windows.

Academic Profile

Course Institution Board/Univ Year of Passing Percentage

M.TECH (DECS) PESIT, Bangalore VTU, Karnataka 2010

70.20%

B.E (ECE)

BTLIT, Bangalore

VTU, Karnataka 2008 60.75%

II PUC LVD college,

Raichur KARNTAKA STATE PU BOARD 2004 59.00%

X STD

ST MARY’S CONVENT HIGH SCHOOL, Raichur

KARNATAKA

STATE BOARD 2002 79.2%

Academic Projects

Project 3: “Design Systolic Array Architecture using Evolutionary Programming”

Project Description: The main objective behind this project is to design systolic array architecture for the regular iterative algorithm using linear mapping techniques and to achieve 100% hardware utilization efficiency by using the concept of evolutionary programming using matlab programming.

Project 2: “Embedded Web Server using 8-bit Microcontroller”

Project Description: Embedded web server using 8 bit microcontroller is an embedded system project using which we can control the operation of any electrical device at home or office remotely. The entire application can be basically divided into two modules “Server” and “Client”. The client in our project is a PC running a web-browser application and should be connected to the server through LAN. The web-server board is an embedded board, which acts as the server in the project. The client is connected to it through LAN. The client is provided with a user interface, where in he is given the facility to turn on or off a device in the form of check box. The client has to check or un-check the check box in order to turn on or off the system.

Trainings and Certifications

”DSP Programming and Applications at IIT Chennai” in the year 2007

Declaration

I hereby declare that the above written particulars are true to the best of my knowledge and belief and I will work with full dedication and sincerity to bring prosperity for the concern.

Yours faithfully,

Suchitra

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