Semiconductor Device Engineer

PROFESSIONAL EXPERIENCE, (**********@*****.***)

• Jun. 2005 – ; Senior Staff Device Engineer, Cypress Semiconductor

- MOSFET and Bipolar device development with 65nm technology

. Mask design for width, length, LOD, well proximity effect, gate capacitance, reliability and mismatch.

. Coordination of the fab process split and automated electrical test on the fabricated wafers.

. Silicon data analysis and modeling spec extraction for the parameters; Vt, saturation Ids, linear Ids, leakage, forward & reverse bias effect and breakdown voltage each for cold/room/high temperature.

. SPICE model creation based on the extracted spec, then SPICE simulation/verification of other bias/operation condition which was not included in electrical test.

. Electrical SPC control target proposal based on Si and model data.

. SPC system setup to monitor Cpk, Z and device properties as lots go through the fab.

. Run bench characterization of the Si device for the electrical test data verification and failure analysis

- High voltage MOSFET development

* Drain-extended structure

. Development of the drain extended high voltage MOSFET on 2.5V(65nm STI process) and 3.3V(0.15um STI process & 0.4um LOCOS process) platforms.

. TCAD optimization with baseline process and device structure design for the required device property.

. Design rule and layer integration verification through DRC, LVS run.

. Data analysis per STI length, channel length/width, gate overlap and gate extension over STI.

. Run minimum design rule verification project including well-well, drain-tap and active rounding effect

. Created automated electrical test program for Vt, Ids, leakage, substrate current, output resistance, sub bias effect and breakdown property.

. Run bench characterization of the Si device for the electrical test data verification and failure analysis.

* LD and JFET drain structure

. LD drain MOSFET development for low gate capacitance SONOS memory cell application on 2.5V STI process.

. JFET-drain structure design for the application of high well doping process with no process change.

- Development of timing control chip using OTP(one time programmable) memory cell.

. Characterizations of OTP cell per temperature, bias and disturb conditions.

. EDR/spec set up and the coordination of the production transfer.

. Development of IBASIC test program which can monitor device reliability(Vt, IDS, IBB) with stress.

- Split gate structure flash memory cell development.

. Characterization/process optimization of flash memory cell with split poly floating gate.

• Mar. 2003 – May 2005 ; Senior Device Engineer, Magfusion Inc,.

- High current capability MEMS structure development.

. Development of low electromigration contact structure and metal line mechanism.

. New contact material and process development for high current mechanical switch.

. Optimization of magnetically actuating mechanical switch performance.

• Jan. 2001 – Feb. 2003; Senior Process Development Engineer, Micron Technology Inc,.

- 0.18um 16Mbit and 0.15um 32Mbit NOR flash memory process development.

. Coordination of new process technology transfer from R&D center to production line.

. Fab process condition and flow set-up for mass production.

. Yield improvement through process condition adjustment and design modification.

. Coordination of design/process/test engineers for the optimization of product performance.

. Process/test data analysis and feedback to design/test engineer for the stabilization of product performance.

. Yield/defect analysis and coordination with process engineer for the corrective actions.

. Run new material/structure and process condition test projects.

• Jan. 1997 – Dec. 2000; Ph.D Student and Research Assistant, Arizona State University.

- Developed the solenoid-type magnetic particle pump for biomedical diagnosis chip application.

- Developed the conducting wire magnetic particle pump.

- Developed low temperature RPCVD silicon dioxide for the application of TFT on plastic device.

- Proposal and feasibility test of electrostatic MicroElectroMechanical micro switch.

• Apr. 1994 – Dec. 1996; Senior Device Design Engineer, Samsung Electronics.

- Designed driver-integrated 10” poly-Si TFT-LCD.

- Optimization of TFT performances for display use.

- Design and characterization of poly-Si TFT-LCD for projection application.

- Designed the driving scheme of driver integrated high-resolution TFT-LCD.

- Managed the development of outer video signal board for projection LCD.

- Development of 0.7”, 3.1”, 2.3” and 5.8” poly silicon TFT-LCD through simulation, design and process optimization.

• Jan. 1987 – Mar. 1994; Device Research Engineer, Samsung Advanced Institute of Technology.

- Design and characterization of Excimer laser recrystallized poly-Si TFT.

- Development of CMOS poly-Si TFT circuit.

- Simulation and optimization of TFT devices and circuits.

- Characterization of TFEL(Thin Film Electroluminescent) Display.

- Development of high voltage EL/PDP driving circuits.

- Simulation and design of liquid crystal light valve.

EDUCATION

• Ph.D: Arizona State University, Jan. 1997 – Dec. 2000.

- Department of Electrical Engineering.

- Dissertation: The Micro-Electromagnetic Particle Pump for Biomedical Application.

• M.S: Kyungpook National University, Korea, Feb. 1987.

- Department of Semiconductor Devices and Materials.

- Dissertation: Hydrogen Spill-over Effect in Pd-gate MOSFET.

• B.S: Kyungpook National University, Korea, Feb. 1985.

- Department of Electrical Engineering

SOFTWARE SKILLS

- Circuit simulation: HSPICE

- Design and Layout editor: CALMA, EDGE, CADENCE

- Process and Device simulation: TSUPREM, MEDICI, PICES

- Magnetic simulation: ANSYS, MAGNETO

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