Digital Design Engineer
Resume:
Aditi Shah
***** ***** ******* **., ******, TX **754
Tel: 510-***-**** Email: *****.*.****@*****.***
SUMMARY: Results driven, creative and highly responsible engineer offering experience in Logic Design and Verification. Enjoys challenging fast paced high tech environment. Works exceptionally well with teams and management. U.S. Citizen.
WORK EXPERIENCE
Freescale Semiconductor: Austin, Texas Mar 2008 – Apr 2009
Logic Design Engineer at Freescale Engineering Rotational Program
Cellular Products Group
• Designed interconnect modules, including RTL coding and block guide creation. Implemented changes to legacy IP.
• Verified IC modules and actively assisted RC and Timing runs for the legacy IP block assuring modules met timing.
• Performed code coverage and added test cases that successfully improved coverage to required percentage.
• Created stand alone test bench for designed interconnect blocks. Performed code coverage analysis and worked with SoC verification team to deliver vectors that apply to the chip level testbench.
• Designed and implemented XML description for new methodology enabling automated RTL, testbench and documentation generation.
• Presented methodology and technical findings to design team providing details on tool operation
Networking and Multimedia Group
• Re-pipelined the Backside L2 (BSL2) cache for e500mc core to efficiently support larger cache sizes and frequency.
• Made size and pipeline enhancements parameterizable and accurately updated relevant documentation.
• Optimized timing by evaluating synthesis and timing reports and then making appropriate logic changes.
• Ensured re-pipelined cache met functional and performance requirements. Debugged failures and fixed logic bugs. Updated and reviewed appropriate latency documentation.
Teaching Assistant for Advanced Digital Design with Verilog and FPGA, Boston University Sept 2007 – Dec 2007
• Created solutions for and graded labs and homework’s.
• Supervised and instructed Xilinx ISE based Labs using Spartan 3E development boards for design testing.
Arshad Electronics Pvt. Ltd.: Mumbai, India (part time) Aug 2005 – May 2006
Design Engineer
• Designed automation systems for packaging machines by integrating sensors and using programmable logic controllers for introducing fault detection schemes. This was done for the induction cap sealing, ozone generator and the Corona treatment machines.
• Implemented a touch-screen user interface panel for user interaction and viewing the operating parameters for the machines.
COMPUTER SKILLS
Languages: Verilog, Veritex, Ladder Logic, XML, Perl, Tcl, SystemC, C/ C++, MATLAB
Tools: Xilinx ISE, ModelSim, Cadence Design Suite, Synopsys DC, Debussy, Stingray, FrameMaker
Other: UNIX/Linux, Microsoft Office
DESIGN SKILLS
-Logic Design -Digital Design for FPGA
-Standalone Module Verification -Timing Analysis
-Embedded Systems Design -Modern Active Circuit Design
EDUCATION
Boston University College of Engineering, Boston MA Jan. 2008
Master of Science in Computer Engineering (GPA 3.68/4.0)
University Of Mumbai, Mumbai India May 2005
Bachelor of Engineering in Electronics Engineering
ACADEMIC PROJECTS
A new Architecture for the CORDIC Algorithm
• Implemented a new architecture for the CORDIC Core processor in Verilog, verified functionality of the Design using ModelSim. Synthesized the design with Synopsys DC and synthesized and optimized the layout with Cadence Encounter.
A Low Power Asynchronous Implementation for the CORDIC Core
• Implemented the unrolled architecture of a CORDIC Core. Synthesized the netlist in Synopsys DC and verified its functionality in ModelSim. Synthesized Asynchronous micro pipeline implementations from Verilog specifications
• Analyzed asynchronous circuit to compare the Quality of Results with its synchronous implementation synthesized for a comparable library
FPGA Implementation of Fano’s Algorithm
• Implemented Fano’s algorithm for encoding and decoding convolutional codes on a Xilinx FPGA development board.
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