JooSang's Resume

JOO-SANG LEE

*** ******* ****** **, ****, NC ****9

919-***-****(H) 919-***-****(C)

*********@*****.***

EXPERIENCE

Senior / Staff Engineer, Infineon / Qimonda, Cary, NC (2001-2008)

- Prepared DfT design for 1G XDR (46n process with open bit line structure)

- Integrated Testmode Block with Rambus serial operation using RTL code

- Invented dq wire test and automatic dummy bitline handling scheme

- Member of Qimonda DfT Verification Expert Group for sharing knowledge and solving bugs

- Member of Test Concept Document Approval Committee for new project setup

- Mentored one Junior Engineer for DfT knowledge transfer

- Successfully Designed GDDR3(+) products : 512M (90n process), 1G (70n process), 1G (70n process with long bit line)

- Improved Testmode Entry Block for High Speed Test

- Developed and Maintained Test Patterns for pre and post RCX Simulation

- Verified Bist Counter for Automatic Internal Address Generation and REDPAD (REDuced connected PAD) Features for Parallel Front Test

- Implemented Data Compression for Internal Write and Expected Read Data, and Compare Result

- Verified Boundary Scan for Ball Connectivity Check

- Simulated DLL off mode operation for Function and Timing Check

- Verified Full-chip Function and Improved Test Patterns for 512M LP DDR and 256M Graphic DDR

- Designed and Verified Testmode for 1G DDR and 256M LP SDR

- Evaluated RC Extraction Procedure Set-up

Senior Engineer, Hynix / LG Semicon, Seoul, Korea (1995-2001)

- Investigated Memory Core Architecture with Team Leader for 144/128M Direct Rambus DRAM

- Led 5 Member Team in Planning and Designing Memory Core

- Coordinated interface between Memory Core and Rambus Interface

- Designed and Layout Column path for 18M Rambus Low Latency and Concurrent version

- Analyzed Failure with Design and Test Team Members

- Completed Full-chip LVS for 18M Rambus DRAM Base version

Design Engineer, Hyundai Electronics, Korea (1986-1987)

- Performed Reverse Engineering (Circuit Extraction and Function Analysis) of 4-bit Micro-Controller

- Carried Block Circuit Simulation and Layout

EDUCATION

MSEE and Finished Ph. D. Coursework, University of Minnesota, Minneapolis, MN (1989-1995)

Research Assistant 5 semesters and Teaching Assistant 2 semesters, GPA : 3.69/4.0

B.S. in Electronic Engineering with Honors, Hanyang University, Seoul, Korea (1982-1986)

Honor Prize 6 times and Scholarship twice, Major GPA : 3.84/4.0

TOOLS

Cadence’s Custom IC Design Environment : Schematic / Layout Editor

HSPICE / Nanosim for Simulation and Verification

DRC / LVS / RC Extraction Experience

C / Perl / Verilog Experience for Test Pattern Creation and Maintenance

PATENT

6 U.S. Patents 6862238, 6653888, 6597622, 6570808, 6529419, 6111798

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