Senior Design Engineer

SANDEEP S.SRIRAM

**** *.**** *****, #*** *******.*****@*****.***

CHICAGO, IL-60616 Contact: 312-***-****

CMOS DESIGN ENGINEER

Over five years of experience in CMOS digital circuit design, circuit simulation, cell level layout and ASIC verification with a broad exposure to sign-off EDA tools. Involved in all the stages of circuit design and fabrication right from specification to packaging and designed various standard cell libraries from 180nm to 45nm using various foundries such as TSMC, IBM and SMC. Seeking a mid-level CMOS design engineering position to contribute in the areas of digital, RFIC and analog circuits as a team player, eventually leading to a technical architect/lead role.

CORE COMPETENCIES

• Design expertise in various standard cell libraries from 180nm to 45nm used in various ARM cores

• Hands-On experience in various EDA tools: Synopsys Hspice, Cadence Spectre, Encounter, Virtuoso, icfb, MAGMA Blast Fusion and Mentor IC Station, Calibre, ELDO spice, MAGMA Siliconsmart, Synopsys DC compiler, Primetime

• Expertise in design and characterization of basic bi-directional I/O buffers used in NEXPERIA chipsets

• Exposure to UNIX shell and PERL scripting

• Ability to mentor and be part of a team in all the stages of CMOS design projects

• Exposure to RFIC and Analog circuit simulations

CERTIFICATIONS

• Post Graduate Diploma in VLSI Design at SANDEEPANI SCHOOL OF VLSI DESIGN Certified by MAGMA, Mentor Graphics and Xilinx

• Deep-Submicron CMOS ICs - Certified by NXP Semiconductors

PROFESSIONAL EXPERIENCE

Research Assistant, Illinois Institute of Technology, Chicago, IL Jan 2010 – Dec 2010

Leading a design effort of Soft Error Immune circuits for latches and SRAM.

Key Accomplishments:

• Designed circuits using UDSM technologies for latch and SRAM

• Created a Netlist for the circuits using HSPICE

• Proposed a novel circuit topology for Soft Error Immune latch and it will be published in ISQED 2011 and ISOCC 2011

• Designed various layouts for basic using cadence icfb

Senior Design Engineer, ARM Embedded Systems, Bangalore June 2008 – July 2009

Developed a set of low power libraries for CMOS045 and CMOS090 standard cells and played a lead role in the design and testing efforts.

Key Accomplishments:

• Led a team of 3 engineers during the development of low power digital cell libraries for 45nm technology base using IBM process nodes

• Designed the standard cells such as nand, nor, flip flop, level shifters and latches for ARM Cortex chip and SAMSUNG chipsets using 45nm process technology

• Drew layouts using Cadence Virtuoso

• Executed DRC and LVS for each circuit using 65nm process technology

• Actively involved in validation tests by instantiating the cells in an ASIC flow using MAGMA and Synopsys tools

• Gained significant experience in performance tests using MAGMA SiliconSmart with a concentration on the key parameters such as delay, power, state dependent leakage, area, setup time, hold time, recovery and removal time

• Gained significant experience in ASIC floor and power planning, clock tree synthesis, STA, LVS, DRC and functionality check

Key Tools used:

• Circuit netlist using Synopsys HSPICE

• MAGMA Blast Fusion and Cadence Encounter for ASIC flows

• Formality for functional verification tests

• Verilog libraries for performing functionality check

Design Engineer, PHILIPS Electronics India Ltd., Bangalore Sept 2005 – May 2008

Designed various general purpose I/O circuits, digital circuits for NEXPERIA chipsets and a transceiver chip containing 70000 gates.

Key Accomplishments:

• Designed general purpose I/O circuits and hysteresis buffers

• Designed digital circuits using 180nm to 65nm process technologies

• Performed characterization of I/O cells and digital standard cells

• Designed a transceiver chip which had 70000 gates in 0.18um technology using TSMC process

• Worked on technologies from 0.18um to 65nm and developed a benchmark ASIC flow and digital cell libraries for PHILIPS in 65nm. Played a key role in achieving a best project team award from the management in 2006

• Got selected for a project out of a team of 25 engineers to work on the layouts libraries using DFM rules instead of conventional DRC to obtain high yield

• Worked closely with Netherlands team during knowledge transfer of DFM project

RESEARCH CONTRIBUTIONS AND IEEE CONFERENCE PAPERS

• Dual loop hardened latch circuit for low power application scheduled for publication in International SOC Design Conference, Korea 2011

• Low power latch design in Near Sub-Threshold Region to improve reliability for soft error scheduled for publication in ISQED, 2011

EDUCATION

Masters in Microelectronics and VLSI, Illinois Institute of Technology, Chicago, IL (expected in 2011)

Bachelors in Electronics and Telecommunications, Vishveshwariah Technological University, India, 2004

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