verilog,system verilog

BEEMREDDY LAKSHMAN

Mobile No-819-***-****,097********

Email **-***************@*****.***,***************@*****.***

CAREER OBJECTIVE:

To secure challenging position where I can effectively contribute my skills as professional, possessing competent technical skills. I would be pleased to work in a professionally managed and growth oriented organization.

EDUCATION QUALIFICATIONS:

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

Year: December 2011.

B. Tech Electronics and Communication Engineering with aggregate 60% from Hasvita Institute of Engineering and Technology (HIET), JNTUH in 2007-2011.

Intermediate with aggregate 70% from Narayana JR. College in 2007.

10th with aggregate 53% from Chalapathi High School in 2005.

Summary of Qualifications:

Good understanding of the ASIC and FPGA design flow

Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification.

VLSI Domain Skills:

HDLs : Verilog.

HVL : SystemVerilog.

Verification Methodologies : Coverage Driven Verification, Assertion Based Verification.

TB Methodology : Basics of OVM Methodology.

EDA Tool : Modelsim and ISE.

Domain : ASIC/FPGA Design Flow, Digital Design. Knowledge : RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis, ABV.

Experience:

December 2011 – April 2012, Maven Silicon, VLSI Design and Training Center

VLSI Projects:

Real Time Clock – RTL design and verification (RTL Design in 10days&verification in 15 days)

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Real Time Clock using Verilog HDL independently

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

Dual Port RAM – verification (verification in 15 days)

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

UART- IP Core – Verification (verification in 25 days)

HVL : System Verilog

EDA Tools: Modelsim.

The UART IP core consists of a transmitter, a receiver, a modem interface, a baud generator, an interrupt controller, and various control and status registers. This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode. It is an interface between wishbone compatible UART transceiver, which allows communication with modem or other external devices, like another computer using a serial cable and RS232 protocol.The UART core RTL is technology independent and fully synthesizable.

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

PROJECTS UNDERTAKEN:

MAIN PROJECT – EMBEDDED ACCESS CONTROL AND SECURITY SYSTEM USING RFID

The objective of this project is when the person enter into the area he must place his RFID card at the reader. The reader reads the tag number and verify the data present inside controller with the respective tag number if the tag number is not valid id does not allows the motor on and does not opens the gate.

MINI PROJECT – MC BASED SOLAR TRACKING SYSTEM

The objective of this project is to track the sun rays and adjusting the solar panel according to their direction in order to absorb most of solar energy.

PERSONAL PROFILE:

Date of Birth : 28-11-1989.

Fathers Name : B.GOVARDHAN REDDY.

Nationality : INDIAN.

Religious : HINDU.

Gender : MALE.

Marital Status : UN MARRIED.

Languages known : ENGLISH, TELUGU.

Hobbies : PLAYING CRICKET, BROWSING, LISTENING TO MUSIC.

I hereby declare that the above mentioned information is correct and true to the best of my knowledge.

PLACE:

DATE:

B.LAKSHMAN

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