Sr .NET Developer /Software Engineer

VINEET MUDGAL

****, *** ****** *** *******, CA o6b36d@r.postjobfree.com +1-213-***-****

EDUCATION

Master of Science – University of Southern California (USC), Los Angeles, CA Aug '09-May '11

Electrical Engineering, Area of concentration: VLSI Design

Courses • Testing of Digital Systems • VLSI System Design-II • VLSI System Design-I • MOS VLSI Circuit Design

• Computer System Organization • Modern Solid-State Devices • Web Technologies • PCB Design Lab

• Solid State Processing and Integrated Circuits Laboratory • Renewable Energy in Power Systems

Bachelor of Engineering – Maharishi Dayanand University, Haryana, India Aug '05- May '09

Specialization in Electronics & Communication Engineering

• Awarded First Class with Distinction.

WORK EXPERIENCE

Web Programmer, USC Marshall School of Business Dec '10- Present

• Working on web project which involve programming, maintaining and design of a data intensive website using HTML, PERL, JavaScript etc.

• Preparing Data sheet and presentations using Microsoft Word, Excel and PowerPoint.

Intern, Akon Electronics India Pvt. Ltd May '08- Aug '08

• Assisted a team of five engineers to complete a project on Electro Static Discharge (ESD).

• Worked on different applications of ESD like Design in Immunity, Static Control Test Station, and Identification of Electrostatic Protected Areas.

COMPUTER SKILLS

• EDA Tools : Cadence6, Design compiler & Prime Time by Synopsys, Cadence Conformal LEC, SOC Encounter, Multisim,

NC verilog, NCSim, Matlab, NanoSim, ChipScope, Spectre, ePD, Hspice, Pspice, ModelSim, Xilinx ISE .

• Hardware description Languages : Verilog, System Verilog.

• Programming Languages/Servers : C, C++, PERL, HTML, CSS, JSP, JavaScript, XML DOM, AJAX, TCL, Apache, Jakarta Tomcat, Netbeans.

• Lab Equipments : Oscilloscope, Function Generator, Multiplier.

• Platforms : UNIX, Windows (XP, Vista, 7), Macintosh.

ACADEMIC PROJECTS

DDR2 SDRAM Memory Controller

• Designing DDR2 SDRAM Memory Controller using Verilog and Synthesizing it using design compiler by Synopsys.

• Implementing initialization, Read/Write and refresh phases in RTL & Post Synthesis of the memory controller.

• Using Synopsys Primetime to generate the Static Timing Analysis (STA) report and Logical Equivalence checking and Place & Route tools

for verification and layout of the design.

The FPGA Test System for Arbitrary Logic Functions

• Lead a team of 5 members to design a Test generation system consisting of Preprocessor, DFT, ATPG, Fault Simulator and Good Circuit Simulator.

• Designed a Parallel Fault Simulator to test a FPGA chip to simulate multiple faults in parallel.

• Determined the faults detected by each test and performed fault dropping for appropriate test patterns.

Full Custom IC Design of 16-Bit Pipelined Multiplier

• Performed circuit level simulation of 16-bit pipelined and un-pipelined Multiplier using CSA and RCA.

• Implemented Layout, Schematic, Place and Route and LVS of 16-bit Multiplier using Cadence.

• Used method of logical efforts to carry out optimal sizing and delay minimization.

Hierarchical Design of Adders

• Dual Rail Adder, 16-bit Carry Select Adder (CSA) and Ripple Carry Adder (RCA) were designed using Cadence Virtuoso Design tools.

• Optimized all the designs and performed LVS and DRC check using Cadence (schematic/virtuoso).

• Simulated the cell layouts and flip-flop schematic using HSpice and reported results in the form of Mwaves/Cscope.

Multi-stage MIPS Pipelined Processor

• Simulated and verified the execution of a 5 stage 20Mhz pipelined processor to support in-order execution of MIPS instructions,

taking care of RAW and Branch hazards with both early and late branching.

• Eliminated data dependent hazards using Forwarding Unit and Hazard Detection Unit.

• Implemented 3 element adder, Multi Cycle CPU and Early branch pipeline processor in the lab design.

Web Scraping – PERL

• Implemented server side script to parse data entered in the forms using regular expressions.

• Used Perl to extract and manipulate the data from finance.yahoo.com and display it on the client side.

Fabrication

• Performed various fabrication processes like Diffusion, Metallization, Photolithography etc, in the Clean Room of ISO Class 100.

• Fabricated Diode, Resistor, Capacitor and MOSFET and electrically Tested and Verified their characteristics.

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