Electrical Engineer

MICHAEL ANDONOV

New York, NY, 212-***-****, cell 973-***-****, **************@*****.***

Summary: Digital Hardware Design Engineer, or ASIC/FPGA Engineer, or Engineering Manager, or Program Manager, or Project Manager. Senior Electrical Engineer with over 15 years experience in research and development involving hardware circuit board designs for a variety of industries: medical, defense, large commercial, and small startups. Designed a wide variety of products for medical device patient monitoring, satellite, wireless, and cellular telecommunications. Excellent digital design skills including schematic capture, ASIC, FPGA, CPLD, microprocessors, VHDL, and Verilog. Power supply, isolated/non isolated DC/DC controllers. Some analog, and RF design. Project management and leadership experience. Venture capital solicitation representative. Prior top secret and SCI security clearances.

PROFESSIONAL EXPERIENCE:

DATASCOPE CORP, Mahwah, NJ Senior Engineer 2002 – 2009

• Hardware Design for a Medical Patient monitoring devices, with annual sales of about 10,000 units a year and which have been selling for about 8 years. Researched 15 microcontrollers, then selected Motorola MCF5282, then redesigned the digital section and the power supply section using 6 linear regulators, 3 buck switching regulators, and one dual rail positive Sepic and negative Cuk switching regulator. On another project, modified a boost PBM pulse burst modulation regulator. Revised the documents: requirements, design, worst case analysis, and test protocol. Used Mathcad extensively to document the regulators, power, and efficiencies of the design.

• Hardware Sustaining Engineering for a Cardiac Assist Balloon Pump with 80% market share. Performed battery runtime measurements and used Mathcad to analyze the data. Debugged AC mains power supply problems and swollen defective Seal Lead Acid batteries.

• Hardware Sustaining Engineering for several products: 1) Bedside monitors which monitor ECG, SpO2, Respiration, Invasive Blood Pressure, Temperature, Carbon dioxide CO2, and Cardiac Output CO 2) a wireless ECG/SpO2 Telepack monitor 3) a wired/wireless Central Monitoring Station. Modified Xilinx and Altera CPLD and FPGA.

• Wrote software validaton protocol procedures for a large Medical Software Central Monitoring Station for controlling wired and wireless patient monitoring devices.

WISCOM TECHNOLOGIES, Clark, NJ ASIC/FPGA Engineer, Senior MTS 2001 – 2002

• Worked on a 3G, WCDMA, 3GPP standard, cellular phone, ASIC chip development. Designed in VHDL a compact 35K logic gate design. This included the complete Downlink Receiver section of the 3GPP spec after the rake receiver symbol combiner. Subsections includes the Viterbi decoder with special Blind mode decoding algorithm, rate matching including derepetition and depuncturing, 1st and 2nd deinterleavers, transport channel multiplexing, and p bit removal. Used tools and devices: Modeltech Simulator, Synplicity synthesizer, Xilinx Project Navigator, Xilinx VirtexE 1000E and 2000E parts. Tested the design with VHDL test vectors and test benches, and with application software in the lab.

• ASIC representative for visits and presentations to 4 Venture Capital Funds to solicit more funding.

LUCENT TECHNOLOGIES, Mount Olive, NJ Hardware Engineer/MTS 1999 – 2001

• Project Lead Hardware design for a circuit board included in a 3G Cellular WCDMA basestation, targeted for the Japanese standard/service provider Docomo. The flexible circuit board populated 12 slots in the rack with slot dependent functions. It also mated to different VME COTS cards (CES RIO2/RIO3) and was considered a Controller assembly when the 2 boards are joined together. The board included: MPC8240 microprocessor, 4 TI Firewire, 2 SMSC ARCNET, 2 UART, a Cypress VME, Live Insertion Quickswitches, Boundary Scan Master, LED’s, Ethernet, DPRAMS, SDRAM, FLASH, 2 Xilinx 95288XL CPLD’s, TTL, LVTTL, GTL, RS485, PECL, and a JTAG scan. CPLD’s designed using Viewlogic Schematic entry, Xilinx synthesis with EDIF, and JTAG port ISP.

LUCENT TECHNOLOGIES, Milpitas, CA Hardware Engineer/MTS 1998 – 1999

• Evaluation of Modems for a LMDS Wireless Broadband System. Compared DVB-S and DVB-C mods and demods from Broadcom, LSI, Sicom, and Sagem. Used Tektronix DVT200 and DDS200 test equipment. Performed BER measurements under several impairments: long cabling, Gaussian noise, poor phase noise. Designed a board for interfacing modem input/output MPEG2 parallel data with a serial BER tester. Evaluation of tools: SPW, Cossap, Xilinx, and Altera.

• FPGA design. Worked on a 16 QAM Modulator board for LMDS applications. Designed using an EPF10K100 part using VHDL, Altera MaxPlus2 schematic, and Matlab. It included an interface to a 70MHz IF Quad digital upconverter AD9856 chip. Implemented a root raised cosine filter using an Altera FIR generator for the I/Q digitally sampled signal.

HYUNDAI ELECTRONICS AMERICA, San Jose, CA Digital ASIC Design Engineer 1996 – 1998

• ASIC designer. Worked on a new architecture development of a CDMA, Qualcomm, IS-95, 150,000 gate, ASIC for hand held, cellular PCS phones. Contributed to architecture definition. Performed Verilog RTL code, synthesis, testbenches, back-end functions of timing analysis, DFT, and gate level simulation. Collaborated on small team on chip integration and verification. Designed specifically the Viterbi decoder, Deinterleaver, De-symbol repetition, Rake fingers, Post synchronized AGC, and Block Phase Estimator blocks. Used SPW software to verify SNR performance of Viterbi Decoder. Tools used: Verilog, Simulators: Cadence Cwaves and Viewlogic VCS, Synopsys Design Compiler and Test Compiler. Achieved 90+ fault coverage with 11 embedded RAMS. Ported several portions to a 100K Altera FPGA.

STANFORD TELECOMMUNICATIONS, Sunnyvale, CA Senior Engineering Specialist 1994 - 1996

• Project Lead Hardware design and manager for a TDMA and VSAT Satellite Burst Demodulator. Managed the program, including 5 engineers and interfaced with many other support people. Performed many system tasks. Designed and tested the main board in the system, which included BPSK/QPSK demodulation, 30 MHz IF down conversion, A/D's, Digital FIR Filtering, 3 Xilinx 4013 FPGA's (performing Decimation/Interpolation, Symbol Synchronization, and Burst Activity Detection), STEL 2211 Block Phase Estimator, 2 NCO/DAC's, 2 Altera 7128E CPLD, 68020 uP, FLASH EPROM, and a standard VME interface. Tools used: Viewlogic for schematic and FPGAs, MAXplus II for CPLDs. Performed BER and system testing, and two 1 week long customer site demonstrations. The system included a VME chassis, a Motorola MVME162 controller card, a PSOS RTOS interface, and a Labview GUI running on a SUN.

• Worked on a CDMA mod/demod wireless local loop project. Modifying 2 Xilinx designs: 4008, 4020E using VHDL, Synopsys compiler, and Model Tech simulator on a SUN.

• Worked on an CDMA mod/demod project called Odyssey for global PCS satellite communications. Designed a CDMA receiver with another engineer. Used ORCAD, Altera 8636 FPGA'S, ADSP-2181, Harris HSP50110 Digital Downconverter, STEL 2410 Correlator/Accumulator, STEL 2211 Block Phase Estimator, Harris HSP43168 Digital Filter.

• Worked on a Spread Spectrum mod/demod project. On the modulator, designed a PN coder chip, including 4 PN coders. Used Actel 1280 FPGA and Viewlogic. Aided the board level designer in design and final system test. Purchased a Nohau 8051 emulator and C debugger. On the demodulator, redesigned several portions of the board and several Actel FPGAs.

• Worked on a GPS Simulator project. Designed a daughter card for the Simulator that included a GPS coder chip performing CA and P code baseband generation. Redesigned this GPS coder chip using an Altera 81188 FPGA.

ESL - A SUBSIDIARY OF TRW, Sunnyvale, CA Senior Engineer 1991 - 1994

• Hardware design and C Programmer. Worked on a Wideband Data Acquisition and Playback project. Designed and tested a SCSI to NuBus circuit card. Performed all hardware and software tasks related to the board. The board consists of a SCSI-2 chip (EMULEX FAS216), 68000 uP, 68440 DMA controller, semi dual port RAM, EPROM’s, PAL'S. Performed schematic design using Mentor Graphics on a SUN. Compiled PAL equations using CUPL. Wrote and tested SCSI protocol firmware in C language using THINK C (Mac) and MRI C and XRAY debugger (386). Tested embedded code using Applied Microsystems 68000 emulator. Investigated and selected the purchase an Applied Microsystems emulator, ANCOT SCSI bus analyzer, 386 computer, MRI C compiler and XRAY debugger.

• Hardware design. Aided in the design and layout of 10 power planes (ECL, Analog, Digital) on a motherboard design. The layout was critical to reducing crosstalk and noise in the high-speed system.

• C Programmer. Wrote C software to test and control several custom made VME circuit boards. Used MRI C compiler and XRAY debugger on a DIGITAL MicroVAX, PSOS+ RTOS was on a MVME167 68040 CPU card. Software modes implemented: built in test, initialization, status, and operational.

• Work order manager for the Analog Recording Subsystem. Wrote government C spec. documentation, interfaced with system engineers responsible for A & B specs. Wrote schedules, cost baselines, and managed budget hours

• Characterized and integrated into system ICS VME A/D vendor board. SNR performance measured using MATLAB FFT plots. Designed an active LPF to cut out test equipment harmonic distortion. Aided the integration of VME SKYbolt i860 and SKYburst vendor boards into system. Utilized C language, SUN, Mac II, VX works MVME147 software. -- Tested a variety of analog active filter boards; repaired a defective STDbus computer; designed PALs using CUPL and DATA I/0.

GTE GOVERNMENT SYSTEMS, Mountain View, CA Engineer 1990 - 1991

• Designed, produced, and tested "Digital Delay Unit", which included a CMOS design circuit card, and power supply. within a rackmount box. Worked on a mission management test bed IRAD project, where researched ADA compiler vendors, Computer graphics vendors, and Workstation vendors, and also produced system drawings.

LOCKHEED ELECTRONICS, Plainfield, NJ Engineer 1988 - 1990

• Responsible for overseeing the project development and installation of satellite signal processing systems. Tested many TTL component circuit cards. Performed site installation, hardware support, and customer interface. Oversaw the ordering of parts, updated schematics and parts lists, and wrote documentation and test procedures. The systems utilized AM Demodulation, FSK, DPSK, time division multiplexing, digital elliptical IIR filters, FIR filters, A/D and D/A conversions, 32 bit multipliers, phase locked loops, VMEbus, IEEE 488, and 68010 CPU board.

FAIRCHILD WESTON SYSTEMS, Syosset, NY Assistant Electrical Engineer Summer intern

• Tested electo-optics circuit boards for military jet cameras.

EDUCATION:

MBA (in progress), Polytechnic Institute of NYU, Brooklyn, NY. GPA 4.0

MS, Electrical Engineering, Polytechnic University, Brooklyn, NY. GPA 3.7

Concentration in Signal Processing and Communications.

Degree includes 4 MSEE transfer courses from Stanford University, Stanford, CA. GPA 3.7

BS, Electrical Engineering, Columbia University, New York, NY

4 Continuing Education courses in Electrical Engineering at 1) Santa Clara University, Santa Clara, CA

and 2) UC Santa Cruz Extension, Santa Clara, CA

Stuyvesant High School, New York, NY

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