Access Control Design

CURRICULAM VITAE

DINESH REDDY MADDEETI

S/o M SAKHA BHUPATHI,

Q. No: B-92, DEEPANJALINAGAR,

NTPC, SIMHADRI, Ph: +91-812*******

VISAKHAPATNAM- 531020. Landline: 089*-******* Andhra Pradesh. Email:***********@*****.***

OBJECTIVE:

Seeking an opportunity to work in an organization, where I can put forth all my strength, Idea & knowledge acquired.

EDUCATIONAL QUALIFICATION:

Class/Course Name of Institute Board/University Year of Passing Marks%

M.Tech

(VLSI Design) Gitam Institute of Technology. GITAM University,

Visakhapatnam. Pursuing (2012) CGPA

7.32

(1st Year)

BE/B.Tech

(Electronics and Communication)

Gayatri Vidya Parishad College of Engineering, Visakhapatnam.

Jawaharlal Nehru Technological University,

Kakinada

2009

62.78

Intermediate Vignan Vidyalayam Junior College,

Visakhapatnam. Board of Intermediate 2005 89.30

SSC Little Angels school,

Ukkunagaram, Visakhapatnam.

State Board Secondary Education 2003 76.50

PROJECTS:

M.Tech (1st Semester):

MIPS (Microprocessor without Interlocked Pipeline Stages) Processor:

The MIPS Processor contains a set of simple arithmetic, logical, memory access, branch, and jump instructions. There are 32 general-purpose register in MIPS, each register is 32 bit wide. The MIPS instructions follow a three-address format: R-format, I-format, J-format .The data path of MIPS consists of Instruction Fetch unit, Instruction decode unit, Instruction execution unit. The instruction execution flow contains 4 steps: 1.fetch instruction 2.decode 3.execution 4.load instruction.

The processor module and the memory are integrated to yield the complete MIPS model. Component descriptions are created for processor and memory unit. These are integrated by using port map statements. Depending upon the synthesis tool; unused signal may be deleted from synthesized tool. The overall MIPS model tested using test bench. The Test bench verify through proper operation of each implemented instruction.

Language Used : Verilog HDL

Tools Used : Cadence Tool

B.Tech (final year):

RFID (Radio-frequency identification) READER DESIGN AT 13.56 MHz:

RFID (Radio Frequency Identification Systems) is one of the most exiting technologies that revolutionized the working practices by increasing efficiencies and improving profitability. It has tremendous application potentials. Radio Frequency Identification systems use radio frequencies to identify, locate and track people, assets and animals. The proposed RFID based system finds applications in detection of theft in a library and access control. The Reader design operates at 13.59 MHz frequency and reads data from an RFID transponder operating at that frequency.

The principle on which the system based is called passive RFID. Passive RFID systems are composed of three main components: Reader, Passive Tag and Microcontroller for data processing. The tag is inserted in the item which is to be detected. When the item enters the vicinity of the reader, it detects the identity of the item. Later, the data acquired by the reader is processed.

TECHNICAL SKILLS:

Languages : C, Verilog HDL, VHDL

Tools : Cadence, Xilinx

ACADEMIC ACHIEVEMENTS:

• Participated in Throttle the Gears in Techkriti 08 – Annual Science and Technology Festival organized by IIT Kanpur.

• Paper published in International Journal of Distributed and Parallel Systems, Volume 2, Number 5, September 2011.

EXTRA CURRICULAR:

• Was a part of the organizing team of X-TRACK’09 a national level hardware expo.

• Was a part of the organizing team of NCCOMTECH a national level technical festival.

PERSONAL PROFILE:

Name : Dinesh Reddy Maddeeti

Date of Birth : 28th August, 1988

Father’s Name : M.Sakha Bhupathi

Mother’s Name : M.Gavaramma

Nationality : Indian

Hobbies : Playing tennis, cricket and listening to music

Languages Known : English, Telugu and Hindi

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Visakhapatnam

Date: Dinesh Reddy. M

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