Signal Processing Software

DUSHYANTH KINJARAPU

**** ******** **** ****, *** 1435, Austin, TX-78749 ******************@*****.*** +1-512-***-****

OBJECTIVE

To seek an Internship position in the field of Hardware Design Programming or core algorithm programming to utilize my skills and experience.

SOFTWARE PROFICIENCY

Programming Languages C, C++, Verilog, LabVIEW, MATLAB.

Operating systems Windows, Unix, Mac

Software Tools Xilinx ISE simulator, Visual studio 2010, gcc compiler, Dev C++.

EDUCATION

• Master of Science in Electrical Engineering GPA 3.83

Concentration: Digital signal Programming University of Texas at San Antonio, USA

• Bachelor of Engineering in Electrical & Communication Engineering GPA 3.66

Concentration: Electronics & Communications Jawaharlal Nehru technological university

PROFESSIONAL EXPERIENCE Duration: 2 years

• Research Assistant

Organization: Graduate Thesis & Research Project, University of Texas at San Antonio

Professor: Dr. David Akopian

SOFTWARE PROGRAMMING APPROACH OF GPS RECEIVER IMPLEMENTATION ON SDR PLATFORMS

• Real time GPS receiver Baseband signal processing algorithm blocks like Acquisition, Tracking implementation in C++ core programming style on Software defined radio Systems.

• Evaluation and Performance analysis of GPS receiver signal processing core algorithms on different software defined radios platforms like Gnu Radio, GPS-SDR, OSSIE (SCA).

• Completed a practical study of each operation of complete GPS receiver Base band signal processing and signal processing in CDMA technology.

HARDWARE PROGRAMMING APPROACH OF GPS RECEIVER IMPLEMENTATION ON SPARTAN-3A FPGA BOARD PRESENT IN USRP RF FRONT- END

GPS receivers Advanced block tracking correlators implementation on SDR RF front end Spartan-3A FPGA of USRP.

Gps tracking correlator Verilog design integration on to the Labview FPGA Single-Cycle Timed loop through IP node integration module.

Implementation of AES (Advanced Encryption Algorithm) Encryption and Decryption on Xilinx Spartan-3A FPGA board.

GPS core algorithm acceleration on hardware using parallel FIFO and Accumulators on FPGA board using Verilog.

Finite state machines control design style coding for proper clock synchronization between the events in these projects.

PUBLICATIONS

A. Suleiman, D. Kinjarapu, D. Akopian “Reconfigurable correlator accelerators for software GPS receivers” Proc of ION GNSS 2011 Conference, September 19-23, Portland, Oregon.

RELATED COURSEWORK

Digital Signal Processing, Foundations of communication Theory, FPGA & HDL Programming, Spread Spectrum & GPS receivers, Signals & Systems, Communications Networking & Security, Wireless communications & Networking, Linear Control Systems.

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