Analog IC Design Engineer

YI HUANG

Address: * ****** ******, **** *********, NY, 11776 • Tel: 631-***-**** • Email: *********@*****.***

OBJECTIVE Seeking a Full Time Position in Analog & Digital IC Design, Testing and Application

EDUCATION

 Master of Science in Electrical Engineering, specialization in Analog IC Design Dec.2008

Stony Brook University (State University of New York at Stony Brook), NY, USA GPA: 3.70/4.0

 Bachelor of Science in Electronic Information Engineering July.2007

Beihang University (National Top Ten Engineering University), Beijing, CHINA GPA: 3.26/4.0

TECHNICAL SKILLS

 Integrated Circuit Design: Cadence Virtuoso

 PCB Design: PADS, Allegro SPB

 Logic Modeling and Verification: Verilog HDL

 Circuit Simulation: OrCAD (PSPICE), ADS

 Programming Language: C/C++, MATLAB

 Digital System Modeling: SystemC, SIMULINK

 Familiarity with Lab Equipment: Oscilloscopes, Multimeters, Function Generators and Logic Analyzers

PROFESSIONAL EXPERIENCE

 Intern Power Electronics Engineer, Aircraft Lighting International, West Babylon, NY, Mar.2008~Dec.2008

 Board level prototyping of an analog fluorescent dimmer and its digital counterpart. PCB layout of the digital dimmer.

 Intern Electrical Engineer, Jona-Group, Huntington Station, NY, Jun.2008~Aug.2008

 Reference design of a finger-controlling optical mouse. Revised the C code of MCU and PCB layout of the product.

IC DESIGN PROJECTS

 A Low-Power Adaptive Continuous Time Filter, July.2008~Dec.2008

 Designed the bandpass Gm-C filter. Low power, nonlinearity cancellation and adaptive technology were used in the OTA.

 Analog Design in Weak Inversion of MOS Transistors, Jan.2008~Mar.2008

 CS Amp and Op Amp circuits were analyzed. The advantage of the gain and of the power dissipation was presented.

 A Fully-Differential Operational Amplifier, Nov.2007~Feb.2008

 Designed a two-stage fully differential operational amplifier with telescopic topology and CMFB.

 SUNY Reduced Instruction Set Computer (RISC) CPU, Sep.2007~Dec.2007

 Bottom-up design of a 16-bit RISC CPU with 5 pipeline stages. The theory of computer architecture was used.

PUBLICATIONS & TECHNICAL REPORTS

 Master Thesis: “Design of Low-Power Adaptive Continuous Time Filters”,2008 Advisor: Dr. M.Stanacevic

 Bachelor Thesis: “A Study on IGES Interface Based on Graphical Electromagnetism”,2007 Advisor: Dr. D.Su

 Y.Xu, H.Xiong and Y.Huang, “Study on Reliability of FC Fabric in Avionic”, ISICT2006 Conference Proceedings

 Technical Report: “Analytical Model Validity in All Regions of the Operation of MOSFET”, May.2008

 Technical Report: “Automatic Timing of an Electrical Outlet implemented by a Microcontroller Unit”, Jun.2005

HONORS, AWARDS & SOCIAL ACTIVITIES

 Provincial Honor: Beijing Excellent Student in Three Aspects (Morality, Academics and Physical Health), Dec.2005

 Highest award for college students. One of four recipients among three hundred and forty candidates in the EE Dept.

 President: Personnel Division of Campus Youth League, EE Department, Beihang University, Sep.2004~Jun. 2006

 One of the top three student leaders in the EE Department. Also organizer of several large scale campus activities.

 3rd Prize (1st Author) of “Feng Ru Cup” (Highest Science and Technology Contest of Beihang University), Jun.2005

 Only 1% of the students can earn a prize. My team was one of the three sophomore winning groups in the EE Department.

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