ASIC Design Engineer

Gita Yellamsetty

*** ******** *****, *******, **, 78023

******.******@*****.***, 210-***-****

Objective

To obtain a position that will utilize my wide breadth of technical skills and aptitude for engineering, while further helping to advance my technical, communicational, and leadership skills.

Education

M.S. in Electrical Engineering, Polytechnic University of New York, GPA – 3.89/4.0 Jan 2010

B.Tech in Electronics & Communication Engineering May 2007

Jawaharlal Nehru Technological University, India, GPA – 3.54/4.0

Software and CAD Tools

Programming: C, C++, MATLAB, 8086 Assembly language, VHDL, Verilog HDL

CAD & Simulation: Cadence Virtuoso Spectre simulator, RTL Compiler, SOC Encounter, NC-Sim, HSpice, ModelSim, Xilinx ISE

Scripts: SKILL-Cadence, Perl

Operating Systems: MS Windows, UNIX

Master’s Thesis

Floorplan based Path Length Optimization Jan 2009 – Dec 2009

for Clos Network-on-Chip (CNoC)

 Proposed a floorplanning algorithm to decrease the length of long interconnection wires for high performance network-on-chip for chip multiprocessor (CMP).

 RTL design of a clos network is synthesized; place and route according to proposed floorplan using SOC encounter and compared with automatic floorplan.

 40% improvement in total wire length and routing area and 58% improvement in critical delay are achieved.

Experience & Projects

Teaching Assistant, Mathematics Department, Jan 2008 – Jan 2010

Polytechnic University of New York

 Tutor/Grader for pre-calculus, Calculus I, II, Differential Equations, Linear Algebra for undergrad students.

Research Assistant, Dept. of Electrical & Computer Engineering, Jan 2009 – Dec 2009

Polytechnic University of New York

 Worked on a flight simulator, a modular display system for insect behavioral neuroscience. Rebuilt the system to display more intensity levels in LEDs by programming microcontroller Atmega168.

System on Chip (SoC) Design of Digital Photo Frame Mar 2009 – May 2009

This photo frame will encode image using JEPG encoder and stores it in memory. The image is decoded and sent to display using a VGA controller. Encoder and VGA controller are IP (Intellectual Property) blocks; decoder is implemented using VHDL.

Supply Voltage Scaling for Optimization of Digital Circuits Oct 2009 – Dec 2009

A 4-bit multiplier circuit is implemented in 45nm technology using Berkeley Predictive Technology Model (BPTM) and optimized with respect to speed and power using voltage scaling technique. Cadence virtuoso spectre circuit simulator is used for implementation and simulations.

Emulation of RC-5 Block Cipher on FPGA Sep 2008 – Nov 2008

RC-5 block cipher is implemented in VHDL, functionality is verified using automated test benches; synthesized using Xilinx ISE web pack. The design is implemented on Xilinx XCS500 FPGA.

Emulation of GrainV1.0 Stream Cipher on FPGA Oct 2008 – Dec 2008

Grain cipher is implemented in VHDL, functionality is verified using automated test benches; synthesized using Xilinx ISE web pack. The design is implemented on Xilinx XCS500 FPGA.

Design and implementation of 16-bit logarithmic Mar 2008 – May 2008

Adder as Brent-Kung Design

Logarithmic adder is implemented using cadence circuit simulator in 180nm technology. Custom layout is drawn using layout editor. Design passed LVS and DRC checks.

VLSI architecture of Image Compression using Verilog HDL Feb 2007 – Apr 2007

JPEG image compression technique is implemented in verilog HDL and the functionality of design is verified using test benches.

Relevant Course Work

Introduction to VLSI Design, Advanced Hardware Design-VHDL, Advanced VLSI Design Techniques, VLSI system & architecture, Analog High Frequency Amplifier Design, RF Electronics, Signals & Systems, Computer Architecture

Languages: English, Hindi and Telugu

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