Design Electrical

Ramu Palaniappan

**** ********* ****, #*****, ******* no: 512-***-****

Richardson Texas – 75080 E-mail: nqjb0u@r.postjobfree.com

OBJECTIVE

Seeking a full-time position in a progressive and forward thinking company where my skills can be utilized to contribute to the success of the organization

EDUCATION

MSEE, Circuits and Systems (GPA 3.52/4.0)

University of Texas at Dallas, Richardson, Texas, USA Aug 2009 – May 2011

B.E, Electronics and Communication Engineering (GPA 81/100)

Anna University, Chennai, INDIA July 2005 – Apr 2009

COURSE WORK

Fall 09 - VLSI, Testing and testable design, Hardware Modeling using HDL

Spring 10 - Advanced VLSI, Advanced Digital Logic, ASIC Design

Fall 10 - Analog Design, Advanced Computer Architecture, Low-Power VLSI Design

Spring 11 - Design Automation of VLSI systems, Microprocessor Systems

TECHNICAL SKILLS

Hardware Description & Programming Languages - Verilog, SystemVerilog, C, Python, Perl, TCL

Operating System - Unix, Linux, Windows, Solaris

Tools - HSPICE ,Cadence, Synopsis, Encounter, Tetramax, Cosmoscope, SimVision, Altera, PrimeTime, Pathmill, Ultrasim, MATLAB, Microwave Office, SPIM simulator, Assura

PROFESSIONAL EXPERIENCE

Intern, IBM India Private Limited May ’10 – August ‘10

India Systems and Technology Lab – Technology Engineering Solutions, Bangalore, India

Single port SRAM Design (Register Files) – [Cadence, HSPICE, Spectre Ultrasim, SimVision]

Worked on bit line voltage regulation, write assist and stability assist of register file

Simulated and analyzed the results for the above instances at 8cpbl, 24cpbl and 128cpbl for decode-2 and decode-8 under various PVT corners using 32nm technology

Performed sigma analysis and analyzed the impact of variation in VT

Worked on compilers and cross section

ACADEMIC PROJECTS

Design of 512-bit SRAM [Cadence, HSPICE, PrimeTime, CosmoScope]

Designed memory cell, row decoder, column decoder, write driver and sense amplifier using 90nm technology. Optimized the design for aspect ratio, area, write time and read time

Design and Simulation of an ASIC Chip in IBM 130nm [Cadence, Encounter, HSPICE, Verilog]

Developed car wash, an FSM machine by creating cell library using cadence, spice simulation, FSM synthesis, timing analysis and placement & routing

Tomasulo Algorithm Simulator [TCL]

Implemented Tomasulo algorithm for dynamic scheduling of instructions and analyzed the tradeoff between performance and resources

Semi-custom Design of 15-bit Multiply and Accumulate Unit [Cadence, Encounter, HSPICE, PathMill, Verilog]

Designed and implemented the layout of 15-bit MAC unit and optimized the design for low power and delay

Implementation of KL algorithm and AMG[C, TCL]

Implemented KL Partitioning and Algebraic Multi-Grid clustering efficiently with reduced time complexity using C and TCL, tested the results for various circuits

Design and Testing of 4-bit Ripple Carry Adder [Verilog, Tetramax]

Designed BIST testable, 4-bit ripple carry adder, using an 8-bit external-XOR LFSR as a pseudorandom pattern generator and 4-bit MISR as a signature compressor

Analysis of Loop Unrolling [SPIM simulator]

Loop unrolling technique was analyzed and compared with unrolled code using SPIM simulator

Design of Asynchronous Fault Detector[Verilog, Synopsys]

Designed and implemented an asynchronous fault detector, which protects an electrical system by buzzing and turning the system off when a fault occurs

MIPS Cross Compiler [GCC , Unix]

Cross compilation to MIPS machine from X86 is done using GCC compiler

Design and Implementation of Two Stage Differential Input and Single-ended Output Op-Amp[Cadence]

Designed an operational amplifier using 130nm technology and achieved an excellent ICMR, CMRR phase-margin and stability

PROFILE

Sound knowledge and hands-on experience in digital logic design, RTL development, functional verification and system level design

Excellent design and debugging skills gained through academic projects and internship experience

Expertise on various facets of electrical concepts and enjoys problem solving

Initiative, agile, self-driven, result-oriented and a dedicated graduate student

AWARDS AND HONOURS

Best Student Award’ for outstanding academic performance in a class of hundred students

Merit Scholarship , a tuition waiver from SSN Institutions for academic excellence

ACTIVITIES

Studied “Static Timing Analysis” course in IBM

Attended seminar on “Open Verification Methodology” conducted by Mentor Graphics

Member of National Cadet Corps (NCC), an organization involved in Army, Navy and Air Force

AVAILABILITY

From June 19th (OPT start date)

REFERENCE

Available upon request

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