Engineer Pvt Ltd

Muralidar.G

E-mail: **********@*****.**.** Ph: 91-994*******

Objective:

Looking forward to work in a challenging role of ASIC verification using HVL based languages and using methodologies as well which makes things easy and increases the product success.

Work Experience:

Worked in IP verification team at Xilinx India Pvt Ltd for 1 year

As a trainee engineer at Xilinx I was given work in various fields which include

• Functional verification with FPGA flow and validation of results

• Writing verilog equivalents for couple of cores

• Worked on GUI testing and verification of IP core GUI’s

• Written test bench environment for “Router” design using system verilog and verified

• Developed generator, monitor and checker components and verified on questasim tool.

• Code coverage and functional coverage done for the design and verified

• Debugged the code and verified

Developed margin systems for virtex 7 devices to meet the requirements

Worked on the project “Design of Configurable Multichannel Interrupt Controller” using AXI bus interface

• Written the code for combination block to combine interrupts

• Used AXI bus protocol in the project to implement. Interrupt priority is configurable for processor by accessing registers through AXI bus interface. Combination interrupt is also realized for one Interrupt Service Routing (ISR) to service multiple interrupts at a time. Up to 60 interrupt inputs and 12 interrupt channels are supported in this design

• Language Used: Verilog

Familiarity with perl in automation for verification environments

• Developed automation flow to run IPs on various platforms.

• Developed cron job to trigger IPs bvt cases automatically once build comes.

• Maintained dashboard checks and updated when required.

Verification of the RTL by running Regressions.

• Analyzed and reported the bugs.

• assisted in debugging the issues

I also gained exposure on team collaboration.

Attended System verilog and OVM training given by XILINX team

Language used : Verilog, PERL

Worked in Prithvi solutions pvt Ltd as a RF Engineer for 1 year

Languages:

1. HDL languages: Verilog, System Verilog

2. Scripting language: PERL

3. Knowledge: TCL,OVM

Tools:

Questasim

Xilinx PlanAhead

Coregen

ISE

Operating System:

Linux

Windows

Education Profile:

• Completed B.Tech in Electronics & Communication Engg from B.V.R.I.T in 2008 and secured 1st class (65.13%)

• Completed Diploma in Electronics & communication Engg from G.M.R.P in 2005 and secured 1st class (76.2%)

• Completed S.S.C from Sri Saraswathi Shishu Mandir in 2002 and secured 1st class(80.6%)

Mini Project:

Title: Speed Checker for Highways

Organization: National symposium ELEKTRA 2K7 conducted at DVRCET.

Description: This circuit is used for measuring the speed of a vehicle. It works on the “principle of LDR”.By using this circuit we can avoid accidents in heavy traffic places.

Achievements:

• Received first prize for paper presentation on “mechanically recorded sound By image processing” at National symposium ELEKTRA 2K7 conducted at DVRCET

• Received Merit Certificate for zone level talent test conducted by the MNR institution.

Strengths:

• Hard Working

• Self Motivated & Determined

• Team Player

Personal Profile:

Name : Muralidhar .G

Father’s Name : Pundareekam

Date of Birth : 25th August 1987

Marital Status : Single

Nationality : Indian

Languages : English, Hindi, Telugu

.

Hobbies : playing and watching cricket, listening to music

Address for Correspondence : H.No:7-108, Opp to Ram Mandir,

Patancheru, Hyderabad

Declaration:

I hereby declare that the above information is true to the best of my knowledge and belief.

Date:

Place:

(G.Muralidhar)

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