Hardware Design Engineer

Professional Experience

July **** to Present

BDKES, LLC

Founder

Hardware design engineering services specializing in all aspects of system, board, and RTL design. Expert in all aspects of system design from initial concept to production. Completed system, board, ASIC, and FPGA designs in the communications, storage, and consumer electronics industries.

Available Services:

• System/Board/FPGA/ASIC design

• Schematic capture with DxDesigner (Viewlogic), Orcad, or Altium.

• Verilog or VHDL RTL design.

• ASIC emulation.

• FPGA design.

• FPGA timing closure.

April 2003 to June 2009

Silicon Image

Sunnyvale, Ca

Member Technical Staff

Part of ASIC design team. Designed numerous high speed Xilinx FPGA based emulation systems for verification of storage and CE ASIC RTL before tape-out. Completed all aspects of emulation system design including architecture definition, schematic capture, layout supervision, and board bring-up. Also responsible for place and route and timing closure of emulation FPGAs. Directly involved in the RTL design and emulation of six separate ASIC product lines which are now in high volume production.

Relevant Skills:

• Working knowledge of various SATA, HDMI, DVI, PCI, USB, and PCI specifications

• FPGA interface to 3Gbps and 6Gbps SATA and HDMI SERDES.

• FPGA interface to 266Mhz DDR SDRAM.

• FPGA interface to 10/100/1G Ethernet.

• Switching regulator and LDO regulator design.

• High speed board design based upon Xilinx Virtex2 and Virtex4 FPGA families.

• Ability to convert standard cell library RTL to Xilinx library RTL.

• Completed FPGA emulation of ASIC designs with over 20 clock domains at speeds greater than 225 Mhz.

January 2002 to April 2003

Transwarp Networks (Acquired by Silicon Image)

San Jose, Ca

Member Technical Staff

Developed an 18 slot high speed chassis based backplane to demonstrate 6 Gbps Communication ASICs which were being developed by other design engineers. Developed a Virtex2 based line card for ASIC emulation before tape out. Part of the ASIC design team for a PCI based 4 Port SATA HBA.

Relevant Skills:

• Performed signal integrity simulation of the backplane design with HyperLynx including conversion of Spice and IBIS models to HyperLynx XTK models.

• Worked with ASIC design team and package vendors to define ASIC system parameters such as pin out, voltage, and package type.

• Familiar with PCI, SATA, and JTAG protocols.

• Developed JTAG, BIST, and external memory interface RTL in verilog for the SATA HBA ASIC.

• Direct experience with NCVerilog, VCS, DxDesigner (Viewlogic), Synplicity, Xilinx ISE, and HyperLynx.

• Performed characterization board design and characterization of 1.5 Gbps SATA Phy.

April 2001 to November 2001

Maple Optical Systems

San Jose, Ca

Sr. Hardware Engineer

Responsible for all aspects of board level design including development of written specifications, component selection, schematic capture, FPGA/CPLD design, board layout supervision, board bring-up, and DVT. Completed several hardware designs as part of the development of the MS3200 Packet Processing Card. This was a highly complex multi-protocol, multi-processor card with 98 separate 2.5Gbit/s links.

Relevant Skills:

• Implemented a Manchester code state machine in a Xilinx CPLD for board to board communication in the system.

• Designed a Quad-Data-Rate (QDR) SRAM interface FPGA daughter board which was used as a precursor to an in house designed ASIC.

August 1998 to February 2001

MAYAN Networks

San Jose, Ca

Sr. Hardware Engineer

Technical lead for a team of hardware engineers developing the MAYAN Unifier platform. The Unifier platform was a highly integrated, multi-protocol, CompactPCI based, access platform that served as the next generation SONET/SDH ADM with integrated functionalities of digital cross-connect, TDM, and Packet switching. Designed the 19-slot CompactPCI/STS-3 backplane for the Unifier. Designed a 28 port DS-1 to VT1.5 line card for the Unifier. Completed a Virtex FPGA design to interface with the backplane’s STS-3 buses and commercially available ICs. This FPGA design was utilized on every line card in the system. All of board and FPGA designs were transitioned to production.

Relevant Skills:

• Key decision maker, along with the CTO, and other lead engineers, on many aspects of the system design.

• Working knowledge of numerous SONET, telecom, and other industry standards including GR-253, ANSI T1.xxx, CPCI, and NEBS.

• VHDL design of FPGAs and CPLDs

• Frequent and proficient use of Orcad schematic capture, Allegro viewer, Synplicity, ModelSim, Xilinx Aliance/Foundation, VxWorks, and Agile software.

• Responsible for board bring up with and without initial firmware using a variety of methods/lab equipment.

January 1996 to August 1998

Telco Systems

Fremont, Ca

Hardware Design Engineer

Responsible for all aspects of embedded processor based board and chip level design. Designed T1/E1 and T1 ADPCM LIUs based upon 8051 and Motorola Coldfire processors. Designed VHDL based programmable logic circuitry utilizing Altera and Xilinx FPGAs/CPLDs. Completed board and system test and design specifications in support of above products. Both products were transferred to volume production.

Relevant Skills:

• Working knowledge of various telecom standards.

• Knowledge of various T1/E1 ICs from Dallas Semiconductor, Brooktree, and other manufactures.

• Drive the products through FCC Part 15 and other homologation requirements.

June 1991 to January 1996

WorldCom

Santa Clara, Ca

Telecommunications Technician

Maintained fiber optic based digital telecommunications equipment including SONET, frame relay, and ATM switches. Performed high capacity digital telecommunications circuit installation and testing.

July 1981 to May 1991

US Navy

NAS Lemoore, Ca

Aviation Electronics Technician (E6)

Numerous assignments and duties including Electronics Instructor and Aviation Electronics Technician. Held US secret clearance.

EDUCATION

BSEE (Cum Laude), San Jose State University, 1995

ADDITIONAL DATA

• Extensive high-speed FPGA design experience including Xilinx Virtex, Virtex-2, Virtex-4, Virtex-5, and Altera families of devices.

• Expert in Xilinx FPGA place and route software and timing closure.

• Extensive microprocessor knowledge including Intel StrongARM, 8051, 80x86, I960, Analog Devices ADSP-2181, and Motorola MPC8260, MPC755, and Coldfire processors.

• Capable of implementing highly complex board/FPGA designs from initial concept to full production in an extremely timely manner.

• Familiar with numerous high speed I/O standards including LVTTL, LVCMOS, LVPECL, SSTL, and others.

Contact this candidate