Engineer Design

Location:

NOIDA, UP, India

Posted:

May 01, 2012

Contact this candidate

Resume:

Gyana Ranjan Sahoo E-Mail: *****.*******@*****.*** Contact: +91-999*******

Professional Preface

A competent and result oriented Product Validation Engineer with 4 years of experience in QA engineer in IC design tools, maintaining QA regression suits, flow validation, verilog coding. Presently working with Cadence Design Systems Pvt. Ltd., NOIDA as Member of Technical Staff.

Areas of Expertise

Technical

Programming Languages :Verilog, Perl Scripting

Semiconductor Industry Tools :Cadence Virtuoso ADE-L, Schematic Editor, AMS Simulator, spetre, ultrasim, layout VLS-L, Design Sync, GDS-II, Tech files, DRC, LVS, XILINX and FPGA .

Platform / Operating Systems :MS-Windows, Linux and Solaris Systems.

Employment Scan

Since June 2010 till date with Cadence Design Systems Pvt. Ltd., NOIDA as Member of Technical Staff

Projects Executed

Title : Flow Testing of Virtuoso Mixed Signal Design Tools.

Description : Involved in product validation of Virtuoso Mixed signal design tools like Spectre, Ultrasim, ADE-L, Schematic-L, AMS simulation & flow validation of different (VCO,PLL) circuits.

Title : Flow Testing of Virtuoso layout Design Tools.

Description : Involved in product validation of Virtuoso back-end tools like Abstract Generator (AG), GDS flow, technology files, LEF files, basic Layout Editor.

Title : Performance Testing of Virtuoso IC6.1.x Tools.

Description : Aim of this project is to test & report performance of various commands used in frontend and backend tools in terms of timings & capacity. For this created various benchmarking flows and automated them.

Since Feb’08 to May 2010 with Cadence Design Systems Pvt. Ltd., NOIDA as Technical Consultant

Projects Executed

Title : Testing of Virtuoso IC6.1.x Tools on different Thin Clients.

Description : Involved in testing of Virtuoso IC6.1.x tools on different Thin Clients like VNC, Citrix, Exceed on Demand (EoD), SunRay, etc. This project involves interactive testing of frontend & backend tools of Virtuoso which run the entire flow which cover all the functionality and features of backend & frontend tools.

Academics Research Work & Projects

Title : Design a Beam-Former in Ultrasound Imaging System in FPGA System (NTU, Singapore).

Description : This project will also involve power consumption evaluation of the various beam-formers to verify the feasibility of portable ultrasound imaging system based on sigma-delta beamforming. In addition, the comparison of the efficiency of real-time delay calculation with pre-calculated delay information stored in lookup table (LUT) is expected in order to select the appropriate one for portable ultrasound imaging system.

Title : Companding Using Mew-Law Algorithm on MXS3FK-004-DSP.

Duration : 2 Months, Place : I2IT, Pune.

Project Team : 2 Members.

Description : The objective of this project is to develop a U-law algorithm in VHDL and port it into Spartan 3 kit.

Title : Designing 16-bit DSP Processor in VHDL using Spartan 3 kit. (MXS3FK-004-DSP).

Duration : 3 Months, Place : I2IT, Pune.

Team Size : 2 Members.

Description : To design a processor that can handle general purpose processor instructions as well DSP Processor instructions. It also produces sine wave, square wave and saw-tooth wave for the testing purposes.

Research & Paper Publication

Title : 16-Bit Floating Point Math Unit for DSP Application.

Highlight : Accepted in International Conference on Computer & Automation Engineering (ICCAE 2010),