Engineer Data

SWETHA R

Contact No: +91-876******* E-mail: ************@*****.***

OBJECTIVE

To build a strong foundation in the design and implementation of Digital and Analog VLSI Integrated Circuits and contribute to the product development objective of the organization and participate in its growth through research and development.

TECHNICAL SKILLSET

Functional Simulation : ModelSim, Isim

Synthesis : Xilinx (FPGA)

Layout : Magic

Hardware Debug tools : Chip scope pro

Digital CMOS design : HSpice

Programming Languages : VHDL, Verilog, C, Microprocessors 8085 & 8086

programming and Interfacing, 8051 Microcontrollers

Multimedia : Adobe and Macro Media tools.

JOB PROFILE

1. Working as ENGINEER in Delopt Pvt. Ltd., from March 2011 – to till date

Works in Delopt

Title : Digital data acquisition system

Team Size : 2

Technology Used : Xilinx ISE 13.1, Chip scope pro, ISIM

Description : This system receives 32 analog (differential) input data which has peak

to peak value of 250mv. This data is fed to four AD9271s. A/D

sampling rate is 6MSPS. The LVDS outputs from the ADCs should

be fed to Vertex5 FPGA. Inside FPGA data is filtered using 14th order

IIR filter. Output of the filter is sampled at 3 MSPS.

Role : Configured 12 bit ADC SPI registers of AD9271 IC using VHDL. It

was tested for both input analog data of 2V and with IO test pattern.

ADC output data was captured on chip scope pro and verified.

Title : Digital data acquisition system

Team Size : 2

Technology Used : Xilinx ISE 13.1, Chipscope pro, ISIM

Role : Designed and implemented data transmission in LVDS mode. Single

ended data was converted to differential signal using OBUFGDS and

IBUFGDS and it was sent through the LVDS cable.

Title : NOR flash

Team Size : 3

Technology Used : Xilinx ISE 13.1, Chip scope pro, ISIM

Description : OMM receives data from 4 different cards (LVDS Channels) based on the

commands given by the homing controller (HC). It operates in 2 modes record

mode and upload mode. The modes of the OMM can be controlled by the GUI

OMM receives commands from the HC. These commands words will be

stored in the NVRAM. Based on the command word OMM receives the data

from the card. In retrieve mode OMM will upload the data from nand flash

path to be uploaded can be selected in GUI. The LVDS channel designed to be

uploaded can also be selected in the GUI.

Role : Designed and coded in VHDL to configure NOR flash to erase, write

and read from the flash. Read data was captured on chipscope and

verified.

Title : Data Pooler Cards

Team Size : 2

Technology Used : Xilinx ISE 13.1, Chip scope pro, ISIM

Description : This card is used in generic for other applications as a data pooler

for the other cards and used for signal processing.

Role : Generated GTP wizard using coregen for 125 MHZ frequency and was

able to transfer the data at the rate of 1.25 gbps with external loopback

using optical fibers which is which is linked via SFP modules.

PUBLICATION

A novel adder cell for leakage current reduction in nanoscale VLSI circuits, IEEE Explore, International conference on Nano-Science Engineering and Technology (ICONSET 2011), November 2011, pp 213-217.

EDUCATIONAL QUALIFICATIONS

Examination

Discipline/ Specialization School/college and University Result in % Year of Passing

B.E. Electronics and communication Engineering Vivekananda Institute of Technology, Visveswaraya Technological University

60.17% 2009

PUC Physics, Maths, Chemistry, Electronics K.L.E Nijalingappa

84.50% 2005

S.S.L.C State Syllabus Cordial High School 90.24% 2003

POST GRADUATE DIPLOMA IN VLSI

Institute Name : CDAC ACTS, Pune.

Modules covered : Advanced digital system design, HDL design using VHDL and

Verilog, Synthesis, System Architecture, ASIC design issues, CMOS

VLSI design (layout and simulation), Verification using System Verilog,

LINUX shell scripting.

Project : A 32 bit five stage pipelined RISC microprocessor architecture.

Team strength : 4

Description : Designed and implemented a 32 bit RISC processor which has direct,

Indirect and immediate addressing modes with arithmetic and logical

Instructions. Processor execution is pipelined in five stages i.e,

Instruction fetch, instruction decode, instruction execution, memory and

Write back stage. Design is done in VHDL and verification in Verilog

Which are simulated using Modelsim and synthesized using Xilinx

FPGA editor.

My contribution : Designed forwarding unit, forwarding unit is necessary since it is a

Pipelined architecture, each stage register contents has to be compared

to decide the further operation to be performed. It was designed using VHDL and simulated in modelsim tool.

CO-CURRICULAR ACTIVITIES & ACHIEVEMENTS

1. Participated in National level technical fest ENGINEER 09 held at NITK Surathkal

2. Participated in International level technical fest APOGEE 09 held at BIT'S PILANI

WORKSHOPS

1. Participated in the short term course under the continuing education program on DSP Programming & Applications from December 7, 2009 – December 19, 2009 conducted by Analog Devices – IIT Madras.

HOBBIES AND INTERESTS

• Robotics

• Reading technical magazines, autobiographies of eminent people and spiritual books

• Chanting Vedas, hymns and bhajans

• Yoga and meditation

• Pranic healing

• Listening to music

• Volunteering for a NGO

PERSONAL DETAILS

Date of Birth : 12th July 1987

Gender : Female.

Nationality : Indian.

Languages Known : English, Hindi,Kannada.

Contact no : 876-***-****

E-mail : ************@*****.***

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