Harsha Vardhan Reddy M
Super Bazar Road,
Kadapa (dist), AP. Email: email@example.com
Pincode: 516360. firstname.lastname@example.org
Seeking a full time position in the VLSI domain to pursue a challenging career in the Design and Verification front.
Class Board/University Year Percentage
M. Tech, VLSI Design. VIT University 2012 8.27/10
B. Tech, ECE JNTU-A University 2010 70.00
12th BIE - A.P. 2006 91.20
10th APBSE (SSC) 2004 86.11
AREAS OF INTEREST:
Digital IC Design
Digital Logic Design
Low power ic design
HDL Known : Verilog
Functional Verification Tool : Modelsim, NC- Sim (Cadence), XILINX ISE 10.2i
Synthesis tool : RTL-Compiler (Cadence)
Back end Tools : SOC Encounter (Cadence)
Layout Tool’s : IC Station (Mentor graphics)
Languages : C,Perl
Presented a paper on “Design of a high gain folded cascade opamp” in international conference on Science, Engineering & Technology at VIT University.
Presented a paper on “Design, Simulation and Verification of the Decoder circuitry for a 64KB SRAM chip” in International conference on Science, Engineering & Technology at VIT University
Presented a paper on “Defense landmine safety system based on wireless technology” at CBIT University.
Title: Implementation of Efficient Motion Search Algorithm In Motion Estimation
A highly efficient algorithm for motion estimation in video coding application is proposed and implemented. The algorithm is intend to reduce the delay, hardware and power requirements than the basic full search algorithm which makes the whole encoder circuitry in video coding complex and inefficient. The successive elimination algorithm is more efficient due to the elimination of the impossible motion vectors in the partial search. The algorithms are implemented using verilog and the comparative parameters are generated using CADENCE RTL compiler in 0.18μm Cmos technology.
Tools: Xilinx, Cadence RTL compiler, Irfan View.
Title: DESIGN OF A DECODER CIRCUITRY FOR A 64KB SRAM ARRAY ARCHITECTURE.
An SRAM array architecture is proposed to reduce the design complexity in the decoder circuitry. The architecture is based on resolving the complex cell array as individual banks that are accessed by the bank selection decoder. The Architecture is designed using Eldo simulator in Mentor Graphics in Cmos 0.18um technology. This architecture provides the ease of accessing each cell in the sram array and reduces the access time in addition to the decoder design complexity.
Tools: Mentor Graphics (Eldo simulator)
A Self biasing technique is implemented to the folded cascode opamp to eliminate the need of the external biasing circuitry without affecting the performance. Gain and voltage swing is increased by using the folded cascode technique on the opamp. Here the circuit is implemented in 0.18um technology using eldo simulator in Mentor Graphics.
Tools: Mentor graphics(Eldo simulator)
Title: Design Of A Gymbyke -Controller From The Specifications. Description:
The Gym-Byke Controller is designed based on the specifications of appropriate Mode selection and Effort level selection. HDL coding is done in Verilog based on the state machine diagram. Simulation is done using Cadence Nc-Sim tool. Synthesis of the HDL file is done using Cadence RTL compiler. Backend process is done using Cadence Soc-Encounter .
Tools: Cadence Nc-sim, Cadence RTL compiler, Cadence Soc-Encounter.
Title: Implementation Of Content Based Speech Water Marking. Description:
In the present technical world, it is always required to secure our digital data from illegal users. One such type of technique is called water marking. Here the Speech Watermarking technique is implemented, where the speech signal is embedded to an audio signal without any adverse effect on the original host signal, so that it acts as a copy protector and a proof of ownership. The embedded speech signal reveals the original owner of the product and thus increasing the digital security.
EXTRA CURRICULAR ACTIVITIES:
Secured 3rd position in the Technical quiz conducted in the college annual festival.
Member of the college cricket team.
Organized national level Tech-fest in my college.
I hereby declare that the above furnished details are genuine to the best of my knowledge.
(Harsha Vardhan Reddy M).