Engineer Design
Resume:
ROBERT L. TOM
San Diego, CA **131
Cell 858-***-****
**************@*****.***
OBJECTIVE
To obtain a position as a Digital Design Engineer utilizing skills developed through my experience and
training in digital design and in debugging.
SUMMARY
More than 10 years experience in designing, implementing, and testing digital circuits using FPGA.
CLEARANCE: Active Secret Clearance
PROFESSIONAL EXPERIENCE
Viasat Inc, Carlsbad, California
Member of Technical Staff, February 2006 - October 2009
* Re designed and implemented Zeroization logic in Verilog on the KG-250A (UAV).
* Created VHDL Test Bench for simulating and debugging Zeroization logic.
* Debugged Alarm issues on Cryptographic units (KG-250 and KG-250A).
* Debugged data flow problems involving encrypting function and decrypting function on the KG-250 using Chip Scope and Modelsim simulations on Xilinx Virtex XC2V1500 and Spartan XC2S300E.
* Debugged and wrote Test Bench for an FPGA Interface using the Xilinx PCI IP core.
* Created test vectors for CESGASS program to test the Security Engine in the Cryptographic Module Assembly.
* Performed feasibility study for replacing FPGAs and CPLDs on the KG-250 to reduce cost of production.
* Supported obsolescence issues affecting the KG-250 and KG-250A.
* Performed ESS testing on new components to ensure compatibility with cryptographic units.
* Debugged hot and cold temperature problems affecting Cryptographic units.
* Written technical notes and reports on problem investigation on KG-250.
* Written Perl scripts to automate programming flash images for the KG-250 and KG-250A.
* Implemented Zeroization FSM design on Xilinx’s XCR3256XL.
* Provided on site technical support to Contract Manufacturer.
Hamilton Sundstrand, San Diego, California
Digital Hardware Engineering Contractor, 2005 - 2006
* Verification of an EDAC circuitry in an Electronic Control Box for an APU unit
* Wrote verification reports and created test stimulus for UUT
* Reviewed EDAC schematics for an APU unit.
Titan Systems Corporation, Scripps Ranch, California
Senior Digital Hardware Engineer, 2001 – September 30th, 2005
* Created schematics to replace legacy ASICS by porting the design to Xilinx FPGA (Virtex 2) and CPLDs on projects such as IDECM (Integrated defensive Electronic Counter Measure).
* Designed state machines that programmed flash memories on board.
* Performed post synthesis, post place and route simulation using Modelsim on VHDL designs.
* Simulated, Synthesized, and Debugged RTL code in FPGA circuits using Modelsim and Synplicity.
* Created programs that generate test vectors in Perl for RTL designs.
* Created microcode compiler using Perl for a processor design.
* Created VHDL Test benches using signal spy and generic vector file input parameters in Modelsim.
* Designed ANSI/IEEE Standard 488.1 (GPIB) interface controller in VHDL.
* Created Client Server style Bus Functional model used in VHDL Test Benches.
* Mentored Junior Engineers in Digital Design and Debug on various projects.
* Provided on site technical support to customer.
BAE Systems, Rancho Bernardo, California
Digital Design Hardware Engineer, 1996 – 2001
* Responsible for designing automatic test equipment for military avionics.
* Designed VXI based digital video translator/generator for RS-343 video display for the Japanese F-2 aviation systems using Xilinx XC4000E.
* Redesigned obsolete ASICS into FPGA in measurement systems for the USAF F-16 IAIS ATE systems.
* Wrote microcode for ALU digital circuits.
* Created programs in C using Visual C++ Studio for generating video test pattern.
* Created ATE programs in C to test circuit boards for sell off.
* Created board schematics using Viewdraw.
* Supported customers by traveling to Japan.
EDUCATION
California Polytechnic State University, Pomona, California
* B.S., Electrical and Computer Engineering, 1995
TOOLS: Modelsim(10 years) , Synplify(10 years), Visual Elite(5 years), Orcad, Xilinx ISE(10 years), Altera Max Plus ][(7 years), Lattice ISP(7 years), Visual C++ Studio(3 years), Perl (5 years ), and EMACS.
OPERATING SYSTEMS: Windows XP, 2000, and Linux Fedora
References will be provided upon request
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