Design Engineer

OBJECTIVE

Seeking a challenging full time position as Design/verification Engineer

EDUCATION

Master of Science, Computer Engineering - May 11

State University of New York at Stony Brook

Bachelor of Engineering, Electronics and Telecommunication Engineering May 09

University of Mumbai, Mumbai, India

SKILLS

• Languages: C, C++, VHDL, Verilog, Perl

• Hardware: Assembly level

• Tools: Cadence(Ncvlog, Ncvhdl, Ncsim, Ncelab), ModelSim, Matlab, EAGLE, Quartus II, LPAD, Visual Studio, Xilinx, Oscilloscope

• OS: Linux, Windows

INDUSTRIAL EXPERIENCE: (IBM, Bangalore, INDIA) Jun 10 – Aug 10

• Position : ASIC Design Intern, India Software Labs

• Responsibilities : 1) Designing De-skewer logic interface in verilog to control delays in the communication channel for ALTERA’s FPGA.

2) Understanding the behavior of the REG ring structure and writing automated verilog test benches to test the functionalities with the error injection and random data writing facility

COURSE WORK

• Computer Architecture Jan 10 – May 10

Designed the full pipelined structure for the Cell SPU processor taking into consideration the various hazards, as well as implementing branch prediction, hardware based speculation and data forwarding in the processor. Project Code was RTL based written in Verilog language, verified using the simulation tool Xilinx.

• Advanced VLSI System Design Aug 09 – Dec 09

Designed a CMOS integrated circuit using the industrial Software CADENCE. Complete work included design using behavioral models as well as learning Design Methodologies, micro architectures, interconnect, packaging, design rules – LVS and DRC.

• VLSI Physical and Logical Design Automation Aug 09 – Dec 09

Designed and implemented state-of-the-art Fiduccia-Mattheyses Algorithm using C++

• Digital Logic Design July 06 – Dec 06

Learning basics of digital logic design like Flip Flops, Latches, Counters, FSMs, Encoders, Decoders and their implementation in verilog.

ACADEMIC RESEARCH Sep 10 – May 11

• Role : Designed a Hand-Held Numeric Breath analyzing Prototype

• Responsibilities: Selecting components for signal detection, amplification, processing and display. Designing the PCB layout from the circuit designed

PUBLICATIONS AND PRESENTATIONS

•First Author paper on “Hand Held Numeric Prototype for Breath Analyzing Sensor Array”, American Institute of Physics, ISOEN May 11

• Poster presentation on ASIC Designing IBM, India Aug 10

• 1st place in Intra – College, IEEE Technical Paper Presentation Competition on ‘MEMS’ Oct 08

READINGS

• Fault Analysis, BIST, Boundary Scan(JTAG), Datastructures Using C and C++(Moshe Augenstein)

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