Rodney K. Rose
Roseville, California 95747
Passionate about delivering advanced technology products at the lowest cost and highest quality. Years of High Tech Industry experience. Expertise includes Intel Management, Intel Quality and Reliability Engineering, and Unisys’ Advanced Packaging Assembly Process Engineering. Certified Lean Six Sigma Black Belt.
Engineering Management Quality Assurance Validation
Program Management Cost Reduction Surface Mount
Product Life Cycle Lean Manufacturing Flip Chip
Assembly Process Engineering LSS Black Belt Reliability
ISO 9001:2008 IPC 610 Mil Std 883.
Engineering Manager - Intel Corporation Thermal Mechanical Group - Folsom, California: 2000 – 2010
Managed team of thermal engineers and lab validation technicians in one of Intel’s most profitable divisions which created processor thermal solutions and shipped more than 12 million units per quarter into the worldwide Channel.
- Product launch schedules met 100% of the time and frequently beat.
- Simultaneously managed an offsite engineering manager and packaging design team.
- Generated thermal roadmaps, provided vision and future direction to the engineering team.
- Collaborated with multi-division thermal teams to create a cohesive virtual team.
- Conducted technology surveys and quality audit inspections of current and prospective overseas High Volume Manufacturing component and assembly suppliers.
- Performed ongoing cost reduction activities successfully meeting goals and saving Intel millions of dollars per year.
- Approved budgets larger than $250K per year which includes lab capital, travel, expense, and big ticket items.
Quality & Reliability Engineer - Intel Corporation - Folsom, California: 1993 – 2000
- Created quality plans and validated assemblies of multiple OverDrive™ processors which included on-package voltage regulation and desktop processor fan heatsink thermal solutions.
- Coordinated mil spec quality analysis and reliability stress testing including mechanical shock, vibration, acoustics, temperature cycling, HAST, power cycling, EMI, MTBF, and cross sectioning.
- Set up and chaired a Quality Advisory Board review process.
- Led Root Cause / Corrective Action task forces. Experienced in FMEA.
- Drove a quality plan for an outsourced mother board and coordinated quality and reliability testing with the supplier.
- Produced quality metrics and Factory First Article Inspection [FFAI] processes at worldwide box assembly sites.
Packaging Assembly Process Engineer - Unisys Corporation - Rancho Bernardo, California: 1984 – 1993
- Surface Mount Assembly: Selected equipment, programmed vision component placement, profiled various reflow systems including IR, convection, H2 furnaces, and vapor phase. Set up and certified assembly processes to military qualification standards. Instituted & directed SPC monitoring. I provided multi-site training to design engineers.
- Developed and certified a process for ball grid array and column grid array assembly onto ceramic packages.
- Introduced a process temperature hierarchy and eliminated process induced failures due to intermetallic compounds on MCM-D thin film ceramic multi chip modules with flip chip assembly.
- Created assembly, reflow, and cleaning processes for custom flip chip multichip modules.
- Utilized full factorial Design of Experiments and the reduced run model by Taguchi to analyze process issues, discover root cause, and provide corrective actions.
Education: Bachelor Science Degree in Metallurgical Engineering, University of Utah, Salt Lake City
- Intel Achievement Award (Highest Corporate Honor)
- Unisys Achievement Award (Highest Corporate Honor)
- US Patent #5810608, Contact Pad Extender for Integrated Circuit Packages
- Chapter Chairman IEEE-Components Packaging & Manufacturing Technology Society San Diego 1992-1993
- Lean Manufacturing and Six Sigma Black Belt Certified
- Eagle Scout