Design Software Engineer

Praveen Kumar Rajamani

****, ** ******* ****, #*** Garden Court, Goleta, CA-93117

Phone: 805-***-****, Email: ***********@*****.***

OBJECTIVE:

To obtain a position in the Hardware field that will help in utilize my potential for the growth of company through my strong educational background and interpersonal skills.

EDUCATION

M.S. Electrical and Computer Engineering GPA:3.47

University of California, Santa Barbara Sep’11 - Oct’12

Relevant Courses:

VLSI Principles, High Speed Digital IC Design, VLSI Testing Technique, Advanced Computer Architecture, Digital design with Verilog,VLSI Project Design, Computer Arithmetic, VLSI Design Validation.

B.E. Electrical and Electronics Engineering Percentage:80/100

Anna University, Chennai, India June’06 - May’10

Relevant Courses:

Power electronics, Microprocessor and Microcontroller, Linear Integrated Circuits, Digital Logic Circuits, Data Structures and Algorithms, Analog Electronics.

TECHNICAL SKILLS

Language : Verilog,C,C++

Design Tools : Mentor Graphics, Matlab, Synopsys, Sue [Schematic Entry Tool], Max [Layout Tool],Hspice

Scripting language:Perl

Simulation Tool: ModelSim,Cosmoscope, Cadence.

Design Skills : ASIC, Digital System,Circuit Design,Layout and Verification.

Operating System: Linux, Windows

Computer Programing: Java, Servlets, JSP

PROJECTS

Schematic and Layout Design of Magnetic Field Effect Sensor MAGFET Apr'12-June'12

• Implemented the MAGFET to measure the differential current from two drains

• did Layout in Cadence of MAGFET and bias network

Implementation of Superscalar Instruction using Completion File in Verilog Feb’12 – Mar’12

• Implemented the functionality of executing dependency of instruction at a time

• Analyzed the use of Completion file and reservation Station

Analytical Characteristics of Nanowire MOSFET Jan’12 - Mar’12

• Analyzed the characteristics of Nanowire MOSFET of 2nm to 4nm radius

• Studied about the minimum supply voltage to drive the Nanowire MOSFET and benefits over Planar MOSFET

Verification and Error injection of OR1200 RISC PROCESSOR Jan’12 - Mar’12

• Converted the RTL in to Gate level netlist of several modules in OR1200 RISC Processor through Design Compiler. Verified the functionality of both RTL and generated gate level net list

• Injected error in to the Gate level net list and Verified with RTL code and coverage is monitored

Implementation of Multilevel Cache in Verilog Jan’12 - Feb’12

• Implemented the functionality of cache in Verilog and tested to get the correct delay in output waveform

• Analyzed the use of Multi level cache in Multi Processor using snoop operation

Design for Testability and Scan design Sep’11 - Dec’11

• Trained to use Mentor Graphics' design for test (DFT) and test generation tools (DFTAdvisor and FastScan)

• Generated test pattern to implement full-scan and partial-scan on an 8-bit RISC microprocessor circuit

64 – Bit Low Voltage Swing Adder Sep’11 - Dec’11

• Implementation of a high-performance adder using low voltage swing (LVS) technology used by Intel in the 90nm node

• Tested the delay made by Passing Carry through logic circuit by giving different set of inputs

Simple Bit Serial Microprocessor Design in Verilog Sep’11 - Dec’11

• Generated the gate level model through Design compiler and compared the Gatelevel and RTL Model

• Output of Gate level Model and RTL Model equivalence was achieved

WORK EXPERIENCE

Assistant Software Engineer Nov’10 - July’11

Tata Consultancy Services, Chennai, India

• Worked as Technical Executive under Nokia Client on Web and Database based issues

• Supported the web pages and database of Nokia Care Warranty and Tested it before moving into production

Project Intern Dec’09 - Mar’10

Neyveli Lignite Corporation Limited, Neyveli, India

• Designed hardware circuit to send multiple data on a single wire to reduce operating costs

• Compiled multiple data from work station and displayed in Unit Control Board.

Summer Intern Apr’09 - June’09

Madras Fertilizers Limited, Chennai, India

• Worked as a trainee in the Generator Service department

• Maintained and Monitored Generator Operations

Grader Jun’25-present

University of California,Santa Barbara

• Worked as grader for Computer science course in University of California

• Graded C programs and used shell scripting to automate it.

Reference:

• Prof. Li-C Wang, Department of ECE

University of California

Tel:805-***-****

mail: *******@***.****.***

• Prof. P. Michael Melliar-Smith

Electrical & Computer Engineering

University of California

Tel: 805-***-****

mail: ****@***.****.***

Contact this candidate