Resume

SAMARSEN REDDY MALLEPALLI

*** ******** ***., *** # *** email:*************@*****.***

Santa Clara – CA 95050 Phone: 573-***-****

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EDUCATION:

M.S. Electrical Engineering Fall 2009 -

ITU-Sunnyvale, USA

M.S. Computer Engineering December 2007

University of Missouri–Rolla (UMR), USA GPA – 4.0/4.0

B.E. Electronics & Communications Engineering July 2002

Osmania University, INDIA GPA – 3.9/4.0

SUMMARY:

• Three years of experience in Computer Engineering.

• In-depth knowledge of Digital Logic circuit design and Optimization using Algorithmic State Machines, State minimization Techniques, Throughput Optimization.

• Good knowledge of Analog circuit design.

• Experience in System-level behavioral, Structural, Data Flow modeling & simulation using Verilog, VHDL.

• Good knowledge of CMOS design, IC (DRC & LVS) layouts.

• In depth knowledge of ASIC design, Validation & Verification flow, Functional and Code coverage.

• Thorough familiarity with Mentor Graphics design tools for schematic entry, layout and functional & post – layout verification.

• Understanding of device parameters with process technologies like TSMC 0.18 microns.

PROFESSIONAL EXPERIENCE:

ASIC DESIGN VERIFICATION ENGINEER – GPG AMD – Feb 2008 – March 2009

• RTL Verification:Created test plans & directed tests and performed simulation & debugging for various Graphics blocks of the next generation GPU’s.

• Modified validation environment for new features.

• Writing tests to verify new features.

• Modified SystemVerilog Functional Coverage model.

• Involved in the development of SystemVerilog test bench using OVM concepts.

• Block & Chip level testing & debugging.

• Modified Clock gating tests to verify new features.

GRADUATE RESEARCH ASSISTANT

University of Missouri – Rolla 2005 - 2007

Libraries and Tools development for Design and Simulation of NULL Convention Asynchronous Circuits:

• Design, optimization, implementation & verification of NCL asynchronous circuits.

• Standard cell library development for NCL gates.

• Transistor level & Physical (CMOS) layout level implementation & verification of NCL asynchronous circuits.

ENGINEER

HAL - India 2003 - 2005 Responsibilities Included:

• Supervising a team of 10 Technicians.

• Design, modification and trouble shooting of RF analog & digital circuits.

• Technical evaluation and scrutiny of quotations for Primary and Secondary Surveillance Radar Systems, Computers and Electronic Measuring equipment.

PROJECTS:

• RTL to physical layout implementation of Asynchronous NULL Convention Logic Quad- Rail (12+4x4) Multiply and Accumulate Unit with TSMC0.18 micron process technology

• Design and implementation of a BIST (built in self test) circuitry for testing a 256x8 RAM.

• Design and Simulation of a Square Root Chip, Run Length Encoder using VHDL, including design and optimization of Data Path and ASM for the system.

• Design and Simulation of a Generic 2’s Complement Dual – Rail NCL Multiply and Accumulate Unit using VHDL.

• Analog Circuit Design - Implementation of Operational Trans-conductance Amplifier

• Programmed 8051 Micro-Controller using Keil C to interface with LCD, mechanical encoder, I2C Bus, IR Remote controller.

SKILLS:

• EDA Tools

• Design: Design Architect, IC Station. Synthesis: Leonardo Spectrum.

• Simulation: Synopsys VCS, ModelSim, QuickSim, AccuSim, HSPICE simulation and analysis, Eldo & Ezwave.

• Design For Test (DFT) Conversant with: Design for Test: DFTAdvisor, FastScan. Memory testing: MBistArchitect.

• HDL, HVL: VHDL, Verilog, SystemVerilog, PSL Assertions

• Programming Languages: C, C++, MATLAB, 8085 and 8051 Assembly Language.

• Operating Systems: Microsoft Windows 9X, XP, UNIX, Sun Solaris 10

PUBLICATIONS & PRESENTATIONS:

S.R.Mallepalli, S.Kakarla, S.Burugapalli, S.Beeerla, S.Kotla, P.Sunkara, W.K.Al-Assadi and S.C.Smith, “Implementation of Static and Semi-Static versions of a 24+8x8 Quad-Rail NULL Convention Multiply and Accumulate Unit” IEEE Region 5 Conference, April 2007

RELEVANT COURSES:

VLSI, VLSI Testing, Analog Circuit Design, Digital Logic, Digital system modeling using VHDL, Computer Architecture & Organization, Microprocessor based design &techniques, Advanced Microprocessors, Embedded Processor System Design, Real-Time Digital Signal Processing.

HONORS & ACTIVITIES:

• Stood among the top 2% in the nation wide Graduate entrance exam for Engineering

• Obtained 534th position (top 0.5%) in state wide Engineering entrance exam

• Executive Committee Member, UMR – INDIA Association.

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