Engineer

NANDYALA MADHU No ***, Flat No ***,

M.E - VLSI Design Vishal Apartments,

3rd Floor, 12th Main,

6th Cross, 5th Sector,

HSR Layout,

Bangalore-560102,

Karnataka

E-mail: *************@*****.***

Mobile:095********/078********

OBJECTIVE

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In search of an entry level position of engineering that will allow me to utilize my engineering skills for company benefit that will also help to improve my career.

PROFILE

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EDUCATION

ME VLSI Design from Kongu Engineering College, Erode, Tamilnadu under Anna University, Coimbatore with 8.11 CGPA passed out June 2010.

BE Electronics and Communications from Sri Chandra Sekharendra Saraswathi Viswa Mahavidyalaya(University), Kanchipuram, Tamilnadu with 7.86 CGPA passed out May 2007.

Intermediate(12th std) from Jupiter junior college, Guntur, Andhra Pradesh under Board of Intermediate Education, AP with 84% passed out April 2003.

SSC from Z P P High School, Rajampalli, Andhra Pradesh under Board of Secondary School Education, AP with 85.50% passed out March 2001.

PUBLICATIONS

“Built in Current Monitor for IDDQ testing with reduced testing time” in Proceedings of “Third National Conference on Communication Technologies 2010(NCCT10)” March 19,20 2010 at Mepco Schelnk College of Engineering, Sivakasi, Tamilnadu

WORKSHOPS ATTENDED

Trained at Tessolve Systems Pvt. Ltd, Bangalore on “VLSI Testing and Circuit Edit” during Masters degree.

Done In-Plant training at BSNL, Vijayawada on Communications during graduation.

ACTIVITIES

Active participant of ECE Association at Post graduate and Graduation levels and took part in the group activities like Organizing committee, Hospitality committee etc.

INTERESTED AREAS

CMOS VLSI Design

ASIC Design.

Digital Design

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SKILL SET

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Circuit Simulators

Microwind

Tanner T-Spice

Quartus II V10

Synopsys VCS, DC Complier, IC Compiler.

HDLs

Verilog HDL

FPGAs

Xilinx Spartan 3E,

Altera DE1.

Platforms

Windows 9x,

Windows 7,

Linux(User).

Programming Languages

C.

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PROJECT WORK

TITLE: AREA EFFICIENT BUILT IN CURRENT SENSOR FOR IDDQ TESTING IN CMOS TECHNOLOGY

Description:

The CMOS circuits needs to be checked for Faults before production. Stuck closed, Stuck open and Gate oxide shorts are common in CMOS circuits. To test for the faults present in CMOS circuits, an approach presented in this project called “IDDQ Testing” where the classification of CMOS Circuits as faulty and non-faulty done by observation of a current IDDQ. This method differs with the conventional voltage testing, but it is faster and precise than the voltage testing.

In this project, a Built in Current Sensor designed with less area requirements. The Built in current sensor measures the IDDQ current present in the CMOS circuits. The Area parameter is very essential with respect to VLSI, it has been taken care in this design. The area of the sensor should not be overhead for the design because the measurement of IDDQ current is on chip measurement. Off chip measurements are also available but they are complex with respect to routing (Capacitance effects). 46% reduction in chip area achieved compared with the existing Sensor.

Role in the Project

Developed various sub blocks of Built-in Current Sensor like Voltage Comparator, Reference Current generator, Test mode selector and Current to Voltage converter.

The Sensor tested for different Circuit Under Test (CUT) like CMOS 2 input XOR gate, CMOS 3 input NAND gate etc.

Made Fault Injection wherever necessary for checking the Built-in Current Sensor operation whether as per the requirement. Made the entire design flexible that it works with any CMOS circuit.

Tools Used and Result

The tool used to implement the BIC Sensor is Tanner version 7.0. The S-Edit is used for schematic entry, W-Edit is used for viewing desired waveforms and T-Spice is used for Spice modeling. The technology used is 180nm.

Results were obtained for different CUTs like 2 input XOR gate and 3 input Nand Gate and classified the circuits as faulty and non faulty.

MINI PROJECTS

• ALU implementation in Verilog HDL.

The ALU design, which holds various functional blocks are designed using Verilog HDL in Modelsim 6.1 circuit simulator in Windowsxp Environment.

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PERSONEL DETAILS

Date of Birth : 21 august 1986.

Sex : Male

Marital Status : Single

Nationality : Indian

Parent’s Name : Mr. Raghava N and Mrs. Asrita Vatsala N

Passport number : G9912580

Languages Known : Telugu, English, Hindi and Tamil(speaking).

HOBBIES

Listening music

Watching Cricket

Playing Table tennis

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REFERENCES

Dr. G.Murugesan,

Professor & Head of the Department

Electronics and Communications Department

Kongu Engineering College,

Perundurai, Erode, Tamilnadu.

Mob : 098********

(NANDYALA MADHU)

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