Analog/Mixed Signal IC Design Engineer

NAVEEN KUMAR DUGGIREDDI

*** * ********** ***. *** 804, Sunnyvale CA 94086 Phone 732-***-**** Email **********@*****.***

OBJECTIVE

To obtain a position as an engineer in the field of Analog/Mixed or Digital IC Design.

Area of Expertise

• 2 years of experience as an Analog/Mixed Signal IC Designer at SIUE IC Design Research Laboratory.

• Co-Authored two publication papers.

• Experienced with designing of Analog/ Mixed Signal Integrated Circuits.

• Analog IC design experience encompassing circuit design, circuit simulation, and physical layout.

• Solid understanding of transistor-level analog circuit design.

• Experienced with Analog blocks such as ADC, DAC, filters, PLL, DLL, power amplifiers, low noise amplifiers, mixers, Bandgap, or Operational Amplifier.

• Basic understanding of continuous- and discrete-time signals and systems

• Proficient in MATLAB, C programming languages and Perl scripting.

• Strong knowledge in analyzing and designing switched capacitor circuits.

• Strong knowledge of Cadence IC design tool kit.

• Good Knowledge in modeling analog and mixed signal components using Verilog and Verilog A.

• Excellent communication skills and the ability to work effectively with cross-site and cross-functional teams.

EDUCATION

Master of Science in Electrical Engineering (May 2011)

Southern Illinois University Edwardsville, IL (GPA: 3.6/4.0)

• Concentration in Analog/Mixed and Digital IC Design.

Bachelor of Engineering, Electronics and Communication Engineering (May 2008)

Anna University, India (GPA: 4.0/4.0)

• Top 2% in the class out of 120 students.

• Best outgoing student Award out of 1000 students.

• Won Prestigious R.M.K scholarship for Outstanding Academic Performance out of 1000 students.

WORK EXPERIENCE

Research Assistant: SIUE IC Design Research Laboratory (May 2009 – April 2011)

Advisor: Dr. George L Engel

• Developing and designing complex, multi-channel, low power Integrated circuits.

• Responsible for all aspects of ASIC design involved circuit design, simulation, checking (DRC and LVS), layout, testing.

• Identified and addressed few performance issues of our First version of PSD8C chip (Pulse Shape Discrimination – 8 Channel) which is a custom ASIC used in nuclear physics experiments.

• Successfully submitted second version of PSD8C (Rev2) for fabrication on 24 May 2010 through MOSIS AMIS C5N run.

• Worked on Xilinx FPGA and helped in layout of another ASIC known as HINP16C chip (Heavy-Ion Nuclear Physics – 16 Channel).

• Work with Cadence Spectre, Virtuoso Layout Editor, Virtuoso AMS Designer, and SoC Encounter tools

• Communicated results effectively by preparing reports and presentations.

• Worked with team of engineers and attended weekly meetings and presentations.

TECHNICAL SKILLS

• Programming Languages : C, C++, Verilog, Verilog-A ,Verilog-AMS and VHDL

• Assembly Languages : INTEL 8085, MOTOROLA 68HC12

• Scripting : Perl, TCL.

• CAD Tools : Cadence Spectre, Virtuoso Layout Editor, Virtuoso AMS Designer, SoC Encounter

• Verification tools : DRC, LVS, Noise.

• Hardware Platforms : 8081, 8085, 68HC12 Microcontroller, Picoblaze, Pacoblaze, Xilinx FPGA

• IDE Tools : Xilinx Embedded Development Kit (EDK), ModelSim, PSpice, MATLAB, MathCAD

• Operating Systems : Linux (Redhat) , Windows, MAC OS ,FreeBSD UNIX

• Other Packages : MS office ,MS Visio

RELEVANT COURSES

Analog CMOS Integrated Circuits Design, Mixed-Signal Design and Modeling, CMOS RF IC Design, Advanced Digital Systems Engineering, High Performance Architecture, Digital VLSI Design, Digital Signal Processing.

MASTER’S PROJECT

Improved Pulse Shape Discrimination System for Nuclear Physics Applications (May 2011)

• Designed digital control circuit for 2nd version of Pulse Shape Discrimination (PSD)

• The source follower buffer was replaced with an amplifier (OTA) connected in a unity gain configuration.

• This removes both the temperature dependence and the charge sharing issues which plagued the initial design.

• Identified cross talk between channels in PSD chip and solved the shared impedance problem.

• Improved noise performance of the integrator in each of sub-channels of PSD chip.

• Increased the multiplicity output range and decreased the overshoot

• Smartly re-layout the new revised TVC circuit and multiplicity output circuit.

• Chip was out in December 2010 and is working great.

ACADEMIC PROJECTS

Design of low power, battery operated ASIC used in Brain Computer Interface (BCI)

• Modeled Chopper Stabilized (CHS) amplifier with gain of 35 and corner frequency of 16 KHz.

• Modeled anti-aliasing filter with gain of 5 and corner frequency of 5 KHz.

• Modeled of 17bit, 250 sample/sec analog-to-digital converter (ADC).

• The ADC will be an oversampling converter (a second order delta sigma design).

Design of Folded-Cascode Operational Transconductance Amplifier (OTA):

• Designed a folded-cascode OTA with a gain of 85 dB, bandwidth of 30 MHz, and phase margin of 60 degrees at transistor level.

• The OTA was fully tested across all corners to meet required specifications.

• Optimized for low noise conditions.

• Physical layout of OTA was completed and tested in AMI 0.5µm process

Design of Bandgap Voltage Reference:

• Designed a bandgap voltage reference of nearly 1.2 volts at transistor level.

• Achieved an error tolerance of less than 0.1% on the band gap reference across all process corners.

• Project involved drawing schematic and testing of circuit across all process corners to meet required specifications in AMI 0.5µm process.

Design of 5-Stage Pipe-Lined Processor:

• A 5-stage pipe-lined RISC processor was designed using Verilog.

• Capable of handling hazards through forwarding and stalling and can start a new instruction on every clock cycle.

PUBLICATIONS

Co-Authored papers

• “Multi-Channel Integrated Circuits for Use in Research with Radioactive Ion Beams”, G. L. Engel, V. Vangapally, N. Duggireddi, L. G. Sobotka, J. M. Elson, R. J. Charity, CAARI Conference, (2010).

(Status: submitted on July 2010: Accepted the proceedings will be published in the American Institute of Physics Conference Proceedings Series).

• “Multi-Channel Integrated Circuits for the Detection and Measurement of Ionizing Radiation”, George L. Engel, N. Duggireddi, V. Vangapally, J. M. Elson, L. G. Sobotka, R. J. Charity, SORMA Conference, (2010).

(Status: submitted on May 2010: Accepted the proceedings will be published in the Nuclear Instruments and Methods (A) Journal (Special Issue on SORMA 2010)).

POSTER PRESENTATION

“Multi-Channel Integrated Circuits for the Detection and Measurement of Ionizing Radiation”, George L. Engel, N. Duggireddi, V. Vangapally, J. M. Elson, L. G. Sobotka, R. J. Charity, SORMA Conference, University of Michigan Ann Arbor (May 2010).

AFFILIATIONS

• IEEE, Student Member

• SIUE Collegiate Entrepreneurs Organization (CEO)-Chief Coordinator.

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