asic verification/design engineer

SUNNY GHOSH

Local Address: Permanent Address:

Om sai ram PG Tata bearings housing complex, Email ID:

Bannerghata rd, Arekere, F-627, Kharagpur, ******************@*****.**.**

Bangalore, Karnataka West Bengal

Ph no-+91-779*******

OBJECTIVE:

To work in a globally competitive environment where I could constantly learn and successfully deliver solutions to problems yielding a steady-pace professional growth and also want to change today’s lifestyle through technology.

Summary of qualifications:

• Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

• Good understanding of FPGA and ASIC design flow.

• Knowledge of Altera quartus, Xilinx, modelsim, Ubuntu.

• Elementary idea of C & data structure.

EDUCATIONAL QUALIFICATIONS:

DEGREE

INSTITUTE

BOARD/UNIV

YEAR

PERCENTAGE

B.E Yeshwantrao Chavan College of Engineering, Nagpur. Nagpur University

2010

Degree-60

XII Kendriya Vidyalaya ,Air force station,

kalaikunda

C.B.S.E

2006

70.20

X Hijli High School, Kharagpur.

W.B.S.E

2004

70.62

EXPERIENCE:

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore.

Position:

Working as a Trainee engineer in ASIC division, from September 2011.

VLSI domain skills:

• HDLs: Verilog and VHDL

• HVL: SystemVerilog

• EDA Tool: Modelsim and ISE

• Domain: Digital Design methodologies

• Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional coverage, Synthesis,

Static Timing Analysis.

VLSI projects:

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Implemented the Real Time Clock using Verilog HDL independently

• Architected the class based verification environment using SystemVerilog

• Verified the RTL model using SystemVerilog.

• Generated functional and code coverage for the RTL verification sign-off & synthesized the design.

Dual Port RAM – verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Implemented the Dual Port Ram using Verilog HDL independently

• Architected the class based verification environment using system Verilog

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL verification sign-off

Video Graphics Adaptor – RTL Design and Verification

HDL: Verilog EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Architected the design

• Implemented the RTL using Verilog HDL

• Verified the RTL using Verilog HDL

• Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board

ENGINEERING PROJECT:

Final year project on Distance measurement using ultrasonic sensor.

TRAINING & EXTRA-CURRICULAR ACTIVITIES:

Industrial training in a division of Tata steel.

Acted in a short film that got viewer’s appreciation award.

Had participated in various seminars.

Was a member of IEEE, sports & spiritual committee.

HOBBIES & INTERESTS:

• Playing cricket, badminton, football.

CORE COMPETENCIES:

• Good communication and adaptation skills.

• Good listener & do things smartly

• Able to work under stress

• Quick & effective learner.

• Adaptable to new environments.

• Good team player & ability to deal with people diplomatically.

PERSONAL PROFILE:

Name : Sunny Ghosh.

Father’s Name : Mr. Dulal Ghosh.

Mother’s Name : Mrs. Ruma Ghosh.

Date of Birth : 08-04-1988

Nationality : Indian

Gender : Male

I hereby declare that all the information provided by me is correct to the best of my knowledge and belief.

Sunny Ghosh

SUNNY GHOSH

Local Address: Permanent Address:

Om sai ram PG Tata bearings housing complex, Email ID:

Bannerghata rd, Arekere, F-627, Kharagpur, ******************@*****.**.**

Bangalore, Karnataka West Bengal

Ph no-+91-779*******

OBJECTIVE:

To work in a globally competitive environment where I could constantly learn and successfully deliver solutions to problems yielding a steady-pace professional growth and also want to change today’s lifestyle through technology.

Summary of qualifications:

• Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

• Good understanding of FPGA and ASIC design flow.

• Knowledge of Altera quartus, Xilinx, modelsim, Ubuntu.

• Elementary idea of C & data structure.

EDUCATIONAL QUALIFICATIONS:

DEGREE

INSTITUTE

BOARD/UNIV

YEAR

PERCENTAGE

B.E Yeshwantrao Chavan College of Engineering, Nagpur. Nagpur University

2010

Degree-60

XII Kendriya Vidyalaya ,Air force station,

kalaikunda

C.B.S.E

2006

70.20

X Hijli High School, Kharagpur.

W.B.S.E

2004

70.62

EXPERIENCE:

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Training Center, Bangalore.

Position:

Working as a Trainee engineer in ASIC division, from September 2011.

VLSI domain skills:

• HDLs: Verilog and VHDL

• HVL: SystemVerilog

• EDA Tool: Modelsim and ISE

• Domain: Digital Design methodologies

• Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional coverage, Synthesis,

Static Timing Analysis.

VLSI projects:

Real Time Clock – RTL design and verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Implemented the Real Time Clock using Verilog HDL independently

• Architected the class based verification environment using SystemVerilog

• Verified the RTL model using SystemVerilog.

• Generated functional and code coverage for the RTL verification sign-off & synthesized the design.

Dual Port RAM – verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Implemented the Dual Port Ram using Verilog HDL independently

• Architected the class based verification environment using system Verilog

• Verified the RTL module using System Verilog

• Generated functional and code coverage for the RTL verification sign-off

Video Graphics Adaptor – RTL Design and Verification

HDL: Verilog EDA Tools: Modelsim, Questa – Verification Platform and ISE

• Architected the design

• Implemented the RTL using Verilog HDL

• Verified the RTL using Verilog HDL

• Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board

ENGINEERING PROJECT:

Final year project on Distance measurement using ultrasonic sensor.

TRAINING & EXTRA-CURRICULAR ACTIVITIES:

Industrial training in a division of Tata steel.

Acted in a short film that got viewer’s appreciation award.

Had participated in various seminars.

Was a member of IEEE, sports & spiritual committee.

HOBBIES & INTERESTS:

• Playing cricket, badminton, football.

CORE COMPETENCIES:

• Good communication and adaptation skills.

• Good listener & do things smartly

• Able to work under stress

• Quick & effective learner.

• Adaptable to new environments.

• Good team player & ability to deal with people diplomatically.

PERSONAL PROFILE:

Name : Sunny Ghosh.

Father’s Name : Mr. Dulal Ghosh.

Mother’s Name : Mrs. Ruma Ghosh.

Date of Birth : 08-04-1988

Nationality : Indian

Gender : Male

I hereby declare that all the information provided by me is correct to the best of my knowledge and belief.

Sunny Ghosh

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