system verilog,verilog,digital,UVM

Vikash Singh

Mobile: +91-767*******~ E-Mail: ***********.****@*****.***

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Seeking entry level assignments in System Verilog / VLSI Design/ ASIC Verification & Design with a growth driven organisation preferably in Electronics & VLSI industry

Location Preference: Bangalore, Chennai,Pune, Hyderabad ,Delhi & Ahmedabad.

Summary

Qualified B.E (Electronics and Comm. Engineering) from Uttar Pradesh Technical University in 2011.

Completed 4 months VLSI Design and Verification course from Maven Silicon VLSI Design and Training Centre, Bangalore.

Possess good understanding of the ASIC and FPGA design flow.

Adept in writing RTL models in Verilog HDL, and Test benches in System Verilog.

Familiar with Industry Standard EDA tools, for the front-end design and verification.

An efficient key player in challenging & creative environments with capacity to adapt to new technologies and skills.

VLSI Domain Skills

HDLs: Verilog and VHDL.

HVL: SystemVerilog and PSL.

Verification Methodologies: Coverage Driven Verification, Assertion Based Verification.

TB Methodology: VMM from Synopsys.

EDA Tool: Modelsim and ISE.

Domain: ASIC/FPGA Design Flow, Digital Design Methodologies.

Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis, Static Timing Analysis.

Academia & Credentials

• B.E (Electronics and Comm. Engineering) from Uttar Pradesh Technical University, Lucknow, India in 2011. Secured 69.06%.

• XII (PCM) from Jamuna Christian Inter College, Allahabad, India in 2005. Secured 62%.

• X from Saraswati Shish Mandir in 2003. Secured 86%.

Other Technical Qualification:

• Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Centre, Bangalore in 2012.

Summer Training

Engineering Project:

Organisation: HPES, NOIDA

Project Title: Vehicle Tracking System with Theft-Protection.

Duration: 2 Months.

Description: Designed microcontroller based system which detected, tracked & gave full information of the vehicle & accordingly controlled the flow of the fuel to stop it in case of theft.

Academic Projects

VLSI Projects

Organisation: Maven Silicon VLSI Design and Training Centre, Bangalore

Title: Real Time Clock – RTL design and verification:

HDL: Verilog

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE.

Details: The responsibilities were:

Used Verilog HDL independently & implemented the Real Time Clock.

Designed the class based verification environment using System Verilog & verified the RTL model using System Verilog.

Synthesized the design & generated functional and code coverage for the RTL verification sign-off.

Title: Video Graphics Adaptor – RTL Design and Verification:

HDL: Verilog.

Tools: Modelsim, Questa – Verification Platform and ISE.

Details: The responsibilities were:

Created the design & devised RTL using Verilog HDL.

Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board.

Personal Dossier

Date of Birth: 15 JAN 1988

Address: #3/7, NGR Complex, Arekere Main Road, BG Road, Bangalore-560076.

Languages Known: Hindi, English.

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