Design Engineer

Santhosh Reddy Addula

Ph No :510-***-**** E-mail: *************.******@*****.***

Objective:

To give my ASIC design career a solid start by joining in a company and contribute to the success of the company by outstanding performances and thereby advancing my career as an IC design engineer.

Profile:

• Hands on experience with Cadence Verilog-XL and Synopsys VCS Verilog simulators

• Good working knowledge on Synopsys Design compiler.

• Hands on experience with FPGA Design by Using Xilinx ISE Design Suite 13.1

• Hands on experience in ATPG methodologies using Design Compiler and TetraMAX.

• Good working knowledge with on Static timing Analysis Using Prime time

• Hands on experience in Place & Route Using Cadence Encounter

• Hands on experience in Schematic drawing for Analog and Digital circuits by Using Cadence Virtuoso 5.1v &6.1v

• Hands on experience in Circuit simulation Using Hspice and Nanosim

• Hands on experience in Physical Verification by using Calibre tool

• Proficient in writing RTL Code using Verilog and VHDL.

• Proficient in Scripting languages in UNIX scripting, Perl and TCL scripting

Academic Projects:

32-Bit Full-Adder Place & Route using Cadence Encounter 10.1V.

● Developed RTL code for 32-bit Full adder

● Logic Synthesis and imported design libraries

● IO placement and block placement

● Power planning and Routing

● IR drop &EM Analysis

● Cell placement, Pre CTS

● CTS (Clock Tree Synthesis) and post CTS.

● Performed Pre Routing and post Routing

● STA (Static Timing Analysis)

● GDS II file generation

11-stage Ring Oscillator Layout Designing Using Cadence Virtuoso 5.1V.

● Designed 11-stage Ring Oscillator schematic by using Cadence Opus.

● Designed Layout for different sizes of inverters using 90 nm technologies

● I have done LVS and DRC Verification.

● Used Extraction for the Layout

● Run simulation for Layout and calculated frequency of the Oscillator.

● Used schematic and generated netlist

RTL Design & Implementation of RISC Processor:

Designing of different modules at RTL and interfacing those using Spartan3E FPGA board acts as a main processor for testing code developed for RISC Processor.

The hardware logic blocks are implemented using VHDL code.

Project Modules: Floating Point Arithmetic unit, Barrel Shifter, Wallace-tree Multiplier.

Education:

Master of Science in Electrical Engineering (Expecting May 2012)

Northwestern Polytechnic University, Fremont, C.A GPA (3.7/ 4.0)

Bachelors in Electronics and Communications Engineering May 2009

CMR Institute of Technology, Hyderabad, INDIA 73.28%

Experience/Skills:

1. Good understanding of the flow of ASIC design from front-end to backend

- Familiar with RTL design using Verilog

- Familiar with Logic synthesis using design compiler

- Familiar with Static Timing Analysis using Prime time.

2. Hands on Experience with DFT Methodologies.

-Familiar with Scan insertion and Scan Analysis.

-Familiar with BIST &ATPG flow using Design compiler and TetraMAX.

3. Hands-on projects of backend design

-Low Power Implementation in 65nm million-gate hierarchical design.

- Through the flow from Netlist to GDS II

- Strong knowledge of floor plan, power plan, placement, Clock tree synthesis, routing, STA, DFM, DFT, LVS, DRC, tape out.

- Familiar with antenna check, signal integrity, IR drop analysis, MSMV, and timing closure

- Using Tcl scripting to simplify the processing of design

4. Solid understanding of semiconductor devices and CMOS

- Understanding full custom design

- Understanding the IC layout and layout rules

- Good at drawing schematic and simulate using Cadence Virtuoso

- Good at building design circuit and simulate using Hspice

5. Working knowledge in Physical Verification using Calibre

-Good understanding in LVS

-Good understanding in Antenna check

-Good at DRC

6. Hands-on experience with FPGA design by using Xilinx ISE Design Suite 13.1

- Understanding of FPGA design flow.

- I have done many academic projects on Spartan3E FPGA board.

7. Teaching Assistant, ASIC design (place and route), 2011

Northwestern Polytechnic University, Fremont, CA.

8. Laboratory Assistant, 2011, Northwestern Polytechnic University, Fremont, CA

- Conducted and managed laboratory sessions; prepared Lab Manual, maintained laboratory equipment and computers.

- Coordinated with instructors to provide lab services to the students; graded homework and lab reports

- Assisted students in Analog Circuits experiments using Hspice & UNIX.

Skills

● Programming/scripting languages: C, C++, Java, Hspice, Perl scripting, TCL scripting, Verilog, VHDL, System Verilog.

● EDA Tools: Cadence Encounter10.1, Virtuoso 5.1, Orcad /Opus, nanosim.

● Synthesis Simulators: Cadence Verilog- XL, Synopsys VCS.

● Synthesis tools: Synopsys Design compiler and Xilinx ISE Design Suite 13.1.

● STA tools: Prime time.

● Operating Systems: Windows 9x/2000/Xp/7, UNIX, Linux.

● Utilities and Tools: Putty, VI, Microsoft Office

● Embedded Environments: MAT LAB, Xilinx.

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