Engineer Pvt Ltd

OBJECTIVE:

To make my knowledge best utilized in the field of Semiconductor business.

PRESENT STATUS [ Aug, 2010 – till date ]

Senior Member of Technical staff, KPIT Cummins Infosystem Ltd, Bangalore, India working for NXP

Semiconductor India pvt ltd, Bangalore.

PROFILE SUMMARY: Professional Experience and Capability

• 5.3 yrs of experience in Full custom layout ( Analog mixed signal and Standard Cells layout ) .

• Hands on experience with leading EDA tools Cadence, Mentor, Assura, PVS, Magma Backend

design and verification tools.

• Worked on latest CMOS process technology from leading Fabs ; TSMC, Dongbu, BCD, FUJITSU,

Global Foundries in technology nodes ( 350nm,130nm, 90nm, 65nm, 45nm,40nm), IBM SOI (45nm).

• Good understanding of Analog Layout Concepts and Issues.

• Experience working with US and UK customers

• Worked with product teams of NXP and Micrel semiconductor.

• Experince in silicon level validation

SKILL SETS:

• VLSI Chip Backend Design : Full Custom Layout, DRC, LVS ,ERC

• Analog Layout Techniques :

a. Matching of Devices : common centroid, interleaving.

b. Shielding.

c. Electro-migration and IR Issues solutions

d. Parasitic extraction.

e. Reliability Issues like Antenna, Latch-up, ESD

f. Methodologies for different types of blocks; half cell symmetry for differential amplifier

• EDA Tools: Cadence (Virtuoso (OA), Virtuoso XL, Spectre, Mentor (IC Station, Eldo, Calibre),

Synopsys (Hercules), Magma (Quartz).

PROFESSIONAL Training Experience

Undergone VLSI Design training (Backend and Front-end) at Sandeepani School of VLSI Design

(Training Div. of CG-Coreel), Bangalore. Duration: Jan’2006 to July 2006

INDUSTRY WORK EXPERIENCE:

• Senior Analog Layout Designer, NXP Contractor

Analog IP’s: Working as an individual contributor to support various analog IP’s for different products.

1. Currently developing Biasing, ringosc, clkcomparator, chargepump,LDO etc blocks in Cmos40nm for

Hemberg product Team . This is required for DC to DC converter.

2. Have developed output buffer, output amplifier and rail to rail output high efficient Class AB amplifier

required for DC brushless motor application as an interface to Instrumentation amplifier.

• Senior Analog Layout Designer, NXP Contractor

1. Worked on the MFIO cells . Layout was already there. My job was to reduce the area .

2. Developed the reference biasing block, LDO, opamp, in the Cmos140nm.

• Senior Analog Layout Designer, NXP Contractor

Done the Validation( testing of chip) for the different IP’s for Cmos40nm process.

• Senior Analog Layout Designer ,Micrel semiconductor ODC KPIT Cummins Ltd. Bangalore, India

Developed the layout of Analog blocks in Dongbu 130nm process like level shifter,cml2cmos,Comparators,bias block, pfd, buffer etc. This projects involves the developing the above Analog blocks. These were the RF blocks so extra care was taken while developing these blocks. Matching,crosstalk, shielding, Electromigartion ,Parasitic cap, routings of the critical signals/nets was the main issues.

My Responsibility includes :

a. Developing the layout as per schematics from the scratch.

b. Floor-planning of devices, Matching of the devices, routing critical signals.

c. Taken care the issues like EM, Cross talk and shielding the signals and guard ring for the sensitive devices.

d. Performed physical verification ( DRC & LVS) with ASSURA.

• Senior Analog Layout Designer,Micrel semiconductor ODC KPIT Cummins Ltd. Bangalore, India

Temp sensor chip: Involved in developing the Temp sensor chip in BCD 035 process. This projects involves

the both Analog and digital blocks. It contained blocks like Oscillator, comparator, Counter, tmp logic, decoder.

The main challenges was the area, matching of the devices, matching of the resistor, Power routings etc.

My Responsibility includes:

a. Developing the block level layouts from the scratch.

b. Floor-planning of devices, matching of the devices, routing critical signals.

c. Layout design, verification ( DRC/LVS)

• Senior Analog Layout Designer,Micrel semiconductor ODC KPIT Cummins Ltd. Bangalore, India

Involved in full chip starting from block level layout to Top level layout. This projects includes both Analog

and digital blocks. It included UVLO, Prereg, Thermprot, comparator, Ibais, Iadjust, divider, Driver, LDO,

bandgap, Current limit ckts , lvlshft ckts Switch ctrl etc It was a full chip projects. So Power routing ,

Matching , Gurard ring ,Shielding and cross talk , EM was the main issues.

My Responsibility includes:

a. Developing the blocks level layout from the schematic

b. Matching the devices, EM, Guard ring implementation, shielding the critical signals.

c. Matching the Resistor and BJT

d. Performed physical verification (DRC & LVS)

• Design engineer , CMR design Automation Pvt Ltd working for Virage Logic,Noida

Role and Responsibility

a. Involved in development of leaf cells layout of Memory compilers .

b. Characterization cells for the extraction purpose.

c. Verification for the Memory layout for different technology.

d. Bit cells application in Mini Array.

e. Generation of Instances and Instances lavel backend Verification (DRC & LVS) of memory compiler

• Layout Engineer, ARM Embedded technology pvt ltd, Bangalore, India

Phase Locked Loop: Developed some Analog blocks like Two stage opamp, differential amp, current

mirror,pfd, charge pump, VCO etc. This was done in TSMC 90nm process. My responsibilities includes

the making of layout from scratch, matching of devices, placement of devices, minimize the parasitic

at critical nodes etc.

• Layout Engineer, ARM Embedded technology pvt ltd, Bangalore,India

Low jitter clock generator &Peak EMI reduction: Developed some Analog blocks like Delay modulation

, voltage regulator, peak detector, PFD , Reference generator etc.

• Layout Engineer, ARM Embedded technology pvt ltd, Bangalore,India

Peak EMI Reduction for power System: Full custom layout of the blocks line VCO,Band gap,Bias Reference Charge pump etc. Main challenges was the matching of devices, placement of the devices and Electromigartion.

• Layout Engineer, ARM Embedded technology pvt ltd, Bangalore,India

Std cell library Developemnt: Worked in various std cells library development starting from 90nm to 45nm for both CMOS and SOI process. This library consists of 8track, 9track and 12 track cells. Main challenges was optimization of area, maintaining the poly pitch & via pitch, pin accessibility.

ACHIEVEMENTS

• Selected for State level scholarship in class 6th & 10th standard.

• Qualified in GATE’ 05

EDUCATION

Bachelor Degree in Electronics & Telecommunication Engineering with 67%

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